Simulation Results: sram_ctrl/main

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.14 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 111.960s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.090s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.380s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 374.150s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 165.350s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1687.400s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 432.770s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2598.000s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1531.360s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 113.050s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1092.610s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 84.730s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 625.240s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 109.780s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 91.260s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 84.950s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1242.680s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.140s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 6765.840s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.080s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.160s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.160s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 115.010s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
sram_ctrl_tl_intg_err 4.440s 0.000us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.440s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1242.680s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1242.680s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1092.610s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1092.610s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1092.610s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 113.050s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 9.500s 0.000us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 115.010s 0.000us 20 20 100.00
sec_cm_mem_readback 36 50 72.00
sram_ctrl_readback_err 11.060s 0.000us 36 50 72.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 111.960s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 111.960s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1092.610s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 113.050s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 111.960s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.130s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 181.890s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 49584317929727223099797015444122739743487035638752761876347595409217739648601 98
UVM_ERROR @ 2736556885 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x52) != exp (0x7f)
UVM_INFO @ 2736556885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 50137768659240259141657256760825565472920342264341470123473263580533521557049 98
UVM_ERROR @ 668939147 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x73)
UVM_INFO @ 668939147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 21471349648082422786183867453908304779168462898874658314511270164676556569659 98
UVM_ERROR @ 711650938 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0xc)
UVM_INFO @ 711650938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30362210072759611927935055442523069435398060748886055621519058078857450430279 98
UVM_ERROR @ 2769294372 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7e) != exp (0x1c)
UVM_INFO @ 2769294372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12106992074966975277676298832343606395857406579044586825025129424354880189269 98
UVM_ERROR @ 2738831276 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3) != exp (0x33)
UVM_INFO @ 2738831276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36747353003431840376141989962761062903400752271171460190661720268532755728684 98
UVM_ERROR @ 2739108068 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x77) != exp (0x5)
UVM_INFO @ 2739108068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30418118008885034069833825168922713768745123661393387796288210847306114746619 98
UVM_ERROR @ 2989356956 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0xb)
UVM_INFO @ 2989356956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 103409442097444302680978979729056479248082059465058476371987508304168292981321 98
UVM_ERROR @ 10943281472 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3f) != exp (0x14)
UVM_INFO @ 10943281472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 8581614069776651378205875884636444463119459434932301535720453053981248951736 98
UVM_ERROR @ 1991712289 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x7c)
UVM_INFO @ 1991712289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 115714026910910777664343429778787360770518246394516933760853097112587016075622 98
UVM_ERROR @ 926695890 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x77) != exp (0x18)
UVM_INFO @ 926695890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 9348718305901083917640353354107538159987083174554319810924032868029979302135 98
UVM_ERROR @ 1370287024 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x22) != exp (0x5e)
UVM_INFO @ 1370287024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 59062090851538008549165846593734924602250695782134445544992831787335851635439 98
UVM_ERROR @ 660131087 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x36)
UVM_INFO @ 660131087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 103019438271826407923122157806695987882710359187520208893492750744445688485004 98
UVM_ERROR @ 5053161072 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x2e)
UVM_INFO @ 5053161072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 113935572532870149381849640116952040993310899570345709221426008822615360297987 98
UVM_ERROR @ 2984741854 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x13)
UVM_INFO @ 2984741854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 88071218548231124371763751608265389365396949059568790028404672780570542053265 100
UVM_ERROR @ 6518169 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6518169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 22803899868781688785368267878841318669918363686831355752735900536866336896342 99
UVM_ERROR @ 6616136 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6616136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 32086438446027174143869025076170682845287308510192373754157111887518907691811 103
UVM_ERROR @ 8479190 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 8479190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 23925980354899334238992586538930624912457780628161721860040700941585290076416 100
UVM_ERROR @ 21559483 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 21559483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 52195369912248455162090200945301524517972281949726393445030128839043559314829 104
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 14869615 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 14869615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 31554994595427161180913893715544804332635001058235630445964234030627578891182 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 666325242 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 666325242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 56562520202558236666852964176369183489334992844393615147054769439923794566611 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 663630712 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 663630712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 88308770763810427961092026666885060351646227903578174772263676811939756494840 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 686858267 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 686858267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 55690264826279505761955908755920436856549317049227031095673410242135483936611 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2739028319 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2739028319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 112036170448490763099610079969462613258722738400428065128480195510167709531803 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2737203090 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2737203090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 89822436853024139704282191077859509692854075847846466726176614152477336569158 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3298428318 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3298428318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 98662013605858000025007366910643754998341707447667087677132965483754937838998 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 690651698 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 690651698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 38904419376307676130347299429694805354017976077815882649729794135399900421315 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 672525760 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 672525760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---