Simulation Results: sram_ctrl/ret

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.13%
V2
100.00%
V2S
93.85%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 90.910s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.770s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 0.820s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 1.570s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 18 20 90.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.410s 0.000us 18 20 90.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 0.820s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 12.080s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 7.020s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1660.630s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 409.670s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 70.960s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1261.650s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 10.640s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1588.970s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 83.710s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 452.410s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 94.390s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 102.500s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 93.440s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1286.390s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.190s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 3525.920s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.020s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 3.530s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 3.530s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.770s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.820s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.930s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.770s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.820s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.930s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.880s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 1.910s 0.000us 20 20 100.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 1.910s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1286.390s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1286.390s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 0.820s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1588.970s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1588.970s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1588.970s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 10.640s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 40 50 80.00
sram_ctrl_mubi_enc_err 1.520s 0.000us 40 50 80.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.880s 0.000us 20 20 100.00
sec_cm_mem_readback 42 50 84.00
sram_ctrl_readback_err 1.500s 0.000us 42 50 84.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 90.910s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 90.910s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1588.970s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 10.640s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 90.910s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.040s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
sram_ctrl_stress_all_with_rand_reset 553.800s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 22926289769428002458078841378805406317676123701724706990562720984809744153748 98
UVM_ERROR @ 103510361 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 103510361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 100272840698993129834266789964240393012648873564372554278547694672569345682115 98
UVM_ERROR @ 97394306 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 97394306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 56977939563666601874711145048345358379225610563285953406410772051371236281679 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 127829565 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 127829565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 55321401379797238221911409375737718340846863088887864257129652577138527408445 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 27697823 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 27697823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 91829964813794995445432418256114521533838056461288531784052531860226376557162 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 45940635 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 45940635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 60292902555569766392972649604260403020267862325440262626584059824867572895885 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 54128214 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 54128214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 69585015563851657548487231925177643702050813928473979143440128648491469531746 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 25817861 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 25817861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 13930933241509528510523632619402216650493383300533408520951018734561355918878 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 110547363 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 110547363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 57147091825591356734941254291425456158327255257311360608710500697236711239249 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 33104292 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 33104292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 33305628271992450261471093063017413956360167061331095521523093622706471620251 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 30914237 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 30914237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 16667493035970472026827379574175045824411693242126618256371285172996155049868 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 30449701 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 30449701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 43189735976129872281520705707583577312127361710204026799935314804228535069414 99
UVM_ERROR @ 6353582 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6353582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 86500642893050238013100590096465118393083421449799653527319107998737072850830 100
UVM_ERROR @ 6429995 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6429995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 84132652994227545592926519425511091407770369733676132759122991462928957926701 99
UVM_ERROR @ 1930087 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1930087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 31802671693235367741334154825236367001741827445499644270943813336824470483778 98
UVM_ERROR @ 90810687 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x72)
UVM_INFO @ 90810687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 8222622998165749419421404975471546663524066004043337396506739107047259802509 98
UVM_ERROR @ 23339059 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x6c)
UVM_INFO @ 23339059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36626495992814916421797425010750250781638174902163318812018128690680730990463 98
UVM_ERROR @ 87717856 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x32) != exp (0x28)
UVM_INFO @ 87717856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 72203035502371235145318861909820067933794008692456191323862728567873669489450 98
UVM_ERROR @ 45812099 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x11)
UVM_INFO @ 45812099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 100236543822270653179899511953483157973311135622938620473810779039989067563844 98
UVM_ERROR @ 46217750 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x79)
UVM_INFO @ 46217750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 110770636629829299873138741056155346573193201792627304559600915097351322576297 98
UVM_ERROR @ 106976575 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x41)
UVM_INFO @ 106976575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 35328217609336680027111961418719354395450849132747317670532844998422074309239 98
UVM_ERROR @ 31711256 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x8)
UVM_INFO @ 31711256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 89914707877401449736147662327791169259933883326015824533300150684543642882824 98
UVM_ERROR @ 24139192 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5f) != exp (0x55)
UVM_INFO @ 24139192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 40720085178367727567446173267803174115927300564259280017800333648807417971940 99
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1843276 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1843276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 108141320097822087456748753863130965860869736975180674992708049322060287749702 101
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 4723876 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4723876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 13103210087767966416050926487435736678198948017183779730354962046601005063177 110
UVM_ERROR @ 850704322 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 850704322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).
sram_ctrl_mubi_enc_err 37082272826300127273820473261288685131493239418079025081427360631302620769451 103
UVM_ERROR @ 29416720 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@4497) { a_addr: 'hb91fd68 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5c a_opcode: 'h4 a_user: 'h2452a d_param: 'h0 d_source: 'h5c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 29416720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---