Simulation Results: adc_ctrl

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.09 %
  • code
  • 98.09 %
  • assert
  • 95.95 %
  • func
  • 19.24 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.63 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.33%
V2S
100.00%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 19.450s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 2.540s 0.000us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 1.680s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 141.370s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 2.520s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.760s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 1.680s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 2.520s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1121.580s 0.000us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1191.670s 0.000us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1282.760s 0.000us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1073.720s 0.000us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1068.350s 0.000us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1545.030s 0.000us 50 50 100.00
filters_both 49 50 98.00
adc_ctrl_filters_both 1432.560s 0.000us 49 50 98.00
clock_gating 38 50 76.00
adc_ctrl_clock_gating 1248.670s 0.000us 38 50 76.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 17.200s 0.000us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 102.170s 0.000us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 419.390s 0.000us 50 50 100.00
stress_all 49 50 98.00
adc_ctrl_stress_all 5059.220s 0.000us 49 50 98.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.740s 0.000us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 1.600s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 2.760s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 2.760s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 2.540s 0.000us 5 5 100.00
adc_ctrl_csr_rw 1.680s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 2.520s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 8.060s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 2.540s 0.000us 5 5 100.00
adc_ctrl_csr_rw 1.680s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 2.520s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 8.060s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_tl_intg_err 14.940s 0.000us 20 20 100.00
adc_ctrl_sec_cm 21.560s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 14.940s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
adc_ctrl_stress_all_with_rand_reset 55.510s 0.000us 48 50 96.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 66874321602698731435858975534187742890052514518034321374309297735481344627365 334
UVM_ERROR @ 216599320924 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 216599320924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 58670149076492842182358669831573825160621049867020171662450728195949921218387 334
UVM_ERROR @ 217803677715 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 217803677715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 29461176022705925253769704425146874831662578089568566628939842804862703471661 323
UVM_ERROR @ 2049020111 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2049020111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 1109865927285644755750103029865344876955926595331222550820291144135610353708 385
UVM_ERROR @ 19886163908 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 19886163908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 113030740223710068177257983466752426407895632215660344881694845571109674035856 317
UVM_ERROR @ 1698106381 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1698106381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 61876229571178695301427543768736725751291983497852567611992449058713194195248 334
UVM_ERROR @ 207132207397 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 207132207397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 84975392418466871252322172114380369810764250491519069744202843999910822169176 345
UVM_ERROR @ 113957149695 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 113957149695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 102537378449507723090955294143017656696826737831350226536494734084423372293356 317
UVM_ERROR @ 2293399548 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2293399548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 91276219347660572484584578784485203356183902340978684694175047193414587773584 334
UVM_ERROR @ 179156738071 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 179156738071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 60193069242155544183830735999178744406408408920383693176101261877379954975292 317
UVM_ERROR @ 15871289816 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 15871289816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 78032933326113763286318835791633886710274907441076715826797411583445793466600 334
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 14221911034528428524241379276042153584841588403963157116440676212329799889545 349
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 110219644049010899806942125917553808181387811306190586682171132706687529400970 351
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 2280032211044005386505439752940049826679739831016942463241687116613784152181 334
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 15615682196057255895293031681882428080440215319709598329970275350390236068996 334
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 17352418008743774320737345412649979671804600572889109296822511418072678595200 317
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---