Simulation Results: clkmgr

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.41 %
  • code
  • 98.93 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.33 %
  • branch
  • 99.15 %
  • cond
  • 96.18 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.12%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.450s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 0.890s 0.000us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 8.390s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.800s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.660s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.800s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.150s 0.000us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.740s 0.000us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.690s 0.000us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.090s 0.000us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.450s 0.000us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 13.470s 0.000us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 11.620s 0.000us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 13.470s 0.000us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 52.010s 0.000us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.380s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 2.970s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 2.970s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 0.890s 0.000us 5 5 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.800s 0.000us 5 5 100.00
clkmgr_same_csr_outstanding 1.860s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 0.890s 0.000us 5 5 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.800s 0.000us 5 5 100.00
clkmgr_same_csr_outstanding 1.860s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
clkmgr_tl_intg_err 4.210s 0.000us 20 20 100.00
clkmgr_sec_cm 3.460s 0.000us 3 5 60.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 3.040s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 3.040s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 3.040s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 3.040s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 17 20 85.00
clkmgr_shadow_reg_errors_with_csr_rw 3.060s 0.000us 17 20 85.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 4.210s 0.000us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 13.470s 0.000us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 11.620s 0.000us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 3.040s 0.000us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.970s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.300s 0.000us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.400s 0.000us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 48 50 96.00
clkmgr_clk_handshake_intersig_mubi 1.380s 0.000us 48 50 96.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.630s 0.000us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
sec_cm_idle_ctr_redun 3 5 60.00
clkmgr_sec_cm 3.460s 0.000us 3 5 60.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.160s 0.000us 20 20 100.00
prim_count_check 3 5 60.00
clkmgr_sec_cm 3.460s 0.000us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 5.590s 0.000us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 149.720s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status
clkmgr_shadow_reg_errors_with_csr_rw 80404167305214546283793073228230087014523829649151546577981800899512834426986 75
UVM_ERROR @ 10784214 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: 0x0 Write_and_check_update_error task: check storage_err status
UVM_INFO @ 10784214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 95332638060476628151417976986935266314607655746747445966163531860622188596896 76
UVM_ERROR @ 128517679 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 128517679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 46573218313795862594637892693844980112799008138661791576563739755806131974348 76
UVM_ERROR @ 164699292 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 164699292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 2152318794359197379683116279392857067335475227043473992954104711312135944480 121
UVM_ERROR @ 62794140 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 62794140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 16005392208851034890776809140564555787202957640608927932212947942494223598917 94
UVM_ERROR @ 22990806 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 22990806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 107525696663098885888751955002214029967378785418552437738288528547120089948172 74
UVM_ERROR @ 4103546 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (3 [0x3] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 4103546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 20729418112844571004046178496535362027423089649856212952056930135600188610253 74
UVM_ERROR @ 60841102 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 60841102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---