Simulation Results: keymgr

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 98.95 %
  • assert
  • 97.72 %
  • func
  • 91.11 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.20 %
  • toggle
  • 98.37 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.17%
V2S
99.32%
V3
64.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 22.090s 0.000us 50 50 100.00
random 50 50 100.00
keymgr_random 31.600s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.190s 0.000us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 13.820s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 6.680s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 1.880s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_csr_aliasing 6.680s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 84.570s 0.000us 49 50 98.00
sideload 200 200 100.00
keymgr_sideload 26.010s 0.000us 50 50 100.00
keymgr_sideload_kmac 56.150s 0.000us 50 50 100.00
keymgr_sideload_aes 29.790s 0.000us 50 50 100.00
keymgr_sideload_otbn 45.170s 0.000us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 17.960s 0.000us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 22.400s 0.000us 48 50 96.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 4.710s 0.000us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 45.910s 0.000us 50 50 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 56.630s 0.000us 49 50 98.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 11.590s 0.000us 50 50 100.00
stress_all 48 50 96.00
keymgr_stress_all 504.200s 0.000us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.080s 0.000us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.210s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.670s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.670s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.190s 0.000us 5 5 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_csr_aliasing 6.680s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 2.380s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.190s 0.000us 5 5 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_csr_aliasing 6.680s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 2.380s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 7.050s 0.000us 20 20 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.240s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.240s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.240s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.240s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.560s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.050s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.240s 0.000us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 84.570s 0.000us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_random 31.600s 0.000us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_random 31.600s 0.000us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 0.000us 20 20 100.00
keymgr_random 31.600s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 22.400s 0.000us 48 50 96.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 56.630s 0.000us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 56.630s 0.000us 49 50 98.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 31.600s 0.000us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 7.150s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 12.510s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 22.400s 0.000us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 12.510s 0.000us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 12.510s 0.000us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 12.510s 0.000us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.470s 0.000us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 12.510s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 32 50 64.00
keymgr_stress_all_with_rand_reset 20.230s 0.000us 32 50 64.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
keymgr_lc_disable 47995114630466027411973616008668936204395850177014521516128971105660518616734 156
UVM_ERROR @ 32268029 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
UVM_INFO @ 32268029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_lc_disable 14080445051334362091901623438953346918685695106322812679288242724187069300557 180
UVM_ERROR @ 22620914 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 22620914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 113948687223898942926204339907250227842473449334279765608743268331343477407397 206
UVM_ERROR @ 200943832 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 200943832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_hwsw_invalid_input 86802255761187099892317236746174817408241762465018160250630631601083055593995 96
UVM_ERROR @ 6414453 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6414453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 23807042807827092882352126763635428349407294310372096334134425688995350061233 1505
UVM_ERROR @ 747467725 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 747467725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 98935969857514175060319960974217187951710427691304919945996126969579827840001 1000
UVM_ERROR @ 1357421597 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1357421597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 59966671731767902073821399615022948576346717512485827945193089788079452072273 436
UVM_ERROR @ 280888491 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 280888491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 60616770795332798483174053140292639859124509096615389949696383996382078582425 603
UVM_ERROR @ 1381376179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1381376179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68025988113734451747595325622062890385240094044602611143885488103916710013837 185
UVM_ERROR @ 227185352 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 227185352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48838015214136717651839337465123375181872324362325859415146183064095241802485 142
UVM_ERROR @ 328508636 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 328508636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85958579171532170521298888871633592538405007940381452778042583716212029056430 334
UVM_ERROR @ 118368987 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 118368987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79503026610984931149746997952320085859489609003052497738279738465139529109780 169
UVM_ERROR @ 101842339 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 101842339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85823970401244727112588413690053497176226056881627359339863387595176832831394 242
UVM_ERROR @ 109424983 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 109424983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 33938567549546685755601825147396799677043278385310894977448919071935880883730 148
UVM_ERROR @ 597193103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 597193103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18696091245296589344669627045130089594077720747003590536629303279021285757315 602
UVM_ERROR @ 1644059040 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1644059040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26878245846397815624848188531280954496305667773709097353809646334613054112345 396
UVM_ERROR @ 174658552 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 174658552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79881329458732038977754768869677928912461857032385695350105322434087749405932 142
UVM_ERROR @ 111601047 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111601047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 29555829177147575788869724737130396281498230475415637911798238027156488594652 282
UVM_ERROR @ 257266699 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 257266699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 35292669509543144651837211561172640822050414045596597974799277820118596757510 182
UVM_ERROR @ 138674220 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 138674220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103688159315048663491665682139984845687758983562879195585451100914866427883920 88
UVM_ERROR @ 119125961 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119125961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103268429961496889796908525113716097690872125688470996677867506103772369776531 717
UVM_ERROR @ 604567432 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 604567432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 22272522409992198068100718166130871596618282572141040934556731814452861181847 128
UVM_ERROR @ 110092116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110092116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 33341508535660278063700243845631710901626302290170502138536867696304314319063 847
UVM_ERROR @ 950377480 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 950377480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
keymgr_kmac_rsp_err 80189145966483107856313018460874119944952467797263859086093870284837595901582 357
UVM_ERROR @ 22372996 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 22372996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start
keymgr_cfg_regwen 26888539964990888049451371257491837583012471998438068777740232180468796661332 264
UVM_ERROR @ 44906867 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 44906867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---