Simulation Results: otbn

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 96.84 %
  • assert
  • 97.16 %
  • func
  • 100.00 %
  • block
  • 99.50 %
  • line
  • 99.66 %
  • branch
  • 93.72 %
  • toggle
  • 93.99 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.71%
V2S
99.32%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
single_binary 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 5.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 6.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 9.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 5.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 6.000s 0.000us 20 20 100.00
otbn_csr_aliasing 5.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 149.000s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 56.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 92.000s 0.000us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 0.000us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 112.000s 0.000us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 117.000s 0.000us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 22.000s 0.000us 60 60 100.00
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 9.000s 0.000us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 20.000s 0.000us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 8.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 6.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 9.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 9.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 5.000s 0.000us 5 5 100.00
otbn_csr_rw 6.000s 0.000us 20 20 100.00
otbn_csr_aliasing 5.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 5.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 5.000s 0.000us 5 5 100.00
otbn_csr_rw 6.000s 0.000us 20 20 100.00
otbn_csr_aliasing 5.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 5.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 28.000s 0.000us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 13.000s 0.000us 5 5 100.00
otbn_controller_ispr_rdata_err 12.000s 0.000us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 0.000us 5 5 100.00
otbn_urnd_err 6.000s 0.000us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 0.000us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 9.000s 0.000us 8 10 80.00
tl_intg_err 25 25 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
otbn_tl_intg_err 98.000s 0.000us 20 20 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 46.000s 0.000us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 28.000s 0.000us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 98.000s 0.000us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 22.000s 0.000us 60 60 100.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 28.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 28.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 22.000s 0.000us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 28.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 9.000s 0.000us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 0.000us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 41.000s 0.000us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 41.000s 0.000us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 0.000us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 12.000s 0.000us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 14.000s 0.000us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 14.000s 0.000us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 26.000s 0.000us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 112.000s 0.000us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 22.000s 0.000us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 85.000s 0.000us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 911.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 578.000s 0.000us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 38486068467752502433202756452190973154650100152996612630195806971829454946731 354
UVM_ERROR @ 1159308863 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1159308863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 17374853166980926504455026286230448872164245201388182601277906503786529053769 522
UVM_ERROR @ 2173528616 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2173528616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 30533224435110243655716745238735488958149688663220185790472576334069823806971 179
UVM_ERROR @ 576705779 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 576705779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19619416747697289896068882648645751358608313766854188804172183816668420294052 156
UVM_ERROR @ 130106933 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 130106933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 48928396819199048815375376307058899901184397782271808562419910645900837541682 175
UVM_ERROR @ 945154602 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 945154602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 53784864457613802304839231572667514956339641688286372178479172042849553436347 168
UVM_ERROR @ 307726994 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 307726994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_zero_state_err_urnd 21129004404458308138720999375026115328841733797226204665022531638512246077708 105
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9600746 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 9600746 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9600746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 51186403442156497825749574361186471368615051574191854759800230082415271467806 117
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32531798 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 32531798 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 32531798 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 32531798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)
otbn_partial_wipe 111658666713239719314329038916428474247562164725564855748272047097356045660353 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,161): (time 10898730 PS) Assertion tb.dut.idle_checker.IdleIfLockedAndNotRotatingKeys_A has failed (3 cycles, starting 10846098 PS)
UVM_ERROR @ 10898730 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 10898730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 6010197530986800888643492682443029511062126774265891216676389551299783042536 114
UVM_ERROR @ 7061294 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 7061294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 49377692421295586146309699156798130254797287486448069782427190603026651616173 86
UVM_FATAL @ 23269265 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 23269265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 33971179071323090000702043283262474591770899996415995251849292987764516045854 86
UVM_FATAL @ 10214892 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10214892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---