Simulation Results: sram_ctrl/main

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.89%
V2S
93.46%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 112.810s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.030s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.060s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.560s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.070s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.070s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.060s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 366.840s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 185.460s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1218.840s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 375.070s 0.000us 50 50 100.00
bijection 49 50 98.00
sram_ctrl_bijection 2505.100s 0.000us 49 50 98.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1300.010s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 118.210s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1277.740s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 108.340s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 638.550s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 91.260s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 105.750s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 106.400s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1378.480s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.080s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7084.790s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.140s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.530s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.530s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.060s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.060s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.040s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
sram_ctrl_tl_intg_err 3.450s 0.000us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.450s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1378.480s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1378.480s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.060s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1277.740s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1277.740s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1277.740s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 118.210s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 12.050s 0.000us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.040s 0.000us 20 20 100.00
sec_cm_mem_readback 37 50 74.00
sram_ctrl_readback_err 8.790s 0.000us 37 50 74.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 112.810s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 112.810s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1277.740s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 118.210s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 112.810s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.000s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 223.170s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 96480188292266026900130536344867653441344905914796515532218435806990575120243 100
UVM_ERROR @ 9785460 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9785460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 96096770042524914029365177295417439400741221380022376726358711566023664643210 99
UVM_ERROR @ 2391084 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2391084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 105981998331678919423855153154011599223172449082547176886467464473303498015945 99
UVM_ERROR @ 4415131 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4415131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 109130678856884679307238591188349655126021033253329726438750595039327842151178 99
UVM_ERROR @ 9510617 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9510617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 33434372671623169836193206316707674211458787671546480577407985291478572496914 99
UVM_ERROR @ 2398213 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2398213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 87298682267765607242770548979273383222517425637047257062603008450139995196741 98
UVM_ERROR @ 2627412077 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x15) != exp (0x2c)
UVM_INFO @ 2627412077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30518571334404347772434134033287886703234866988707112151579380351474422197227 98
UVM_ERROR @ 658644469 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x3d)
UVM_INFO @ 658644469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 96879970325136579525518061951577576230426667713754658137635164408026640402357 98
UVM_ERROR @ 2740393067 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0x42)
UVM_INFO @ 2740393067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 22586869602692090165909496085232430693034172397746210040268840758160566485383 98
UVM_ERROR @ 1568385329 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x13)
UVM_INFO @ 1568385329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 90468417495743603593176847724343212102256046464056895025654569567587336449004 98
UVM_ERROR @ 1368298814 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7a) != exp (0x30)
UVM_INFO @ 1368298814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 1909442222059431114188058523871662709498180182305729399451023006338548439066 98
UVM_ERROR @ 1325791801 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x7f)
UVM_INFO @ 1325791801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 80163033339345158052073757714925595426466398241160504180688076046128012568385 98
UVM_ERROR @ 2745365132 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x17)
UVM_INFO @ 2745365132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 4960763982850220333776139784088955880635767970855758068993656406425379823299 98
UVM_ERROR @ 707694734 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x21) != exp (0x4c)
UVM_INFO @ 707694734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 87821363086089990900489050502852168065966541108756709639405766778285625128414 98
UVM_ERROR @ 685254545 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x15)
UVM_INFO @ 685254545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 87889797434064190720522864351055038592980681755076931344992543380479944642450 98
UVM_ERROR @ 2641361849 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x15)
UVM_INFO @ 2641361849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 5207133886181251252158546068997030079632942598524934201799046613193548376027 98
UVM_ERROR @ 722959104 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x4a)
UVM_INFO @ 722959104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 56312712673918599804674736810505097527136818569159750707575656517381291543442 98
UVM_ERROR @ 686688155 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x5b)
UVM_INFO @ 686688155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 50858936123315211502220097761455939872251356038680868037037800433100945128746 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3463714346 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3463714346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 14503725764072787216327902559976079085106132869093550053648207004530488717046 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 5051107738 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 5051107738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 51002518489042418273723164505520645578055212539737071007887828091726372453241 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3086948434 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3086948434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 115364857561147446266004360700114670483344297720278007441335003906581724527681 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 658163045 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 658163045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 21730079392576551916780778521104915733113557680849009865243465494292278822586 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 684719152 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 684719152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 45208783468893948655278187777364596721044282685111783688725710195101852433443 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1050245882 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1050245882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 4502097085317924059682126559674446490485345230126413292366585922065579843505 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3287735977 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3287735977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 2457757597722109778550750618441920271083497235052809188032269765791888255822 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1278706609 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1278706609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
sram_ctrl_bijection 97697631763815168319742627210980362315314142560323637419951945243250590909712 96
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).
sram_ctrl_readback_err 65751673021462182487259721406093400289594818311878004059094858173339517019662 98
UVM_ERROR @ 1380853089 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@6033) { a_addr: 'h567ebc48 a_data: 'h7b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h1 a_user: 'h26ef6 d_param: 'h0 d_source: 'h28 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 1380853089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---