Simulation Results: sram_ctrl/ret

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.57%
V2
100.00%
V2S
93.59%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 104.690s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.010s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.130s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.160s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.440s 0.000us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.130s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 12.770s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 8.660s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1305.690s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 384.040s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 80.180s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1659.610s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 13.080s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1368.060s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 97.540s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 535.170s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 102.790s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 99.660s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 105.670s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1224.170s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.180s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 4404.630s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.550s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.550s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.010s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.130s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.260s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.010s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.130s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.260s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.250s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 2.970s 0.000us 20 20 100.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 2.970s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1224.170s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1224.170s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.130s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1368.060s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1368.060s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1368.060s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 13.080s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 45 50 90.00
sram_ctrl_mubi_enc_err 1.560s 0.000us 45 50 90.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.250s 0.000us 20 20 100.00
sec_cm_mem_readback 35 50 70.00
sram_ctrl_readback_err 1.470s 0.000us 35 50 70.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 104.690s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 104.690s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1368.060s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 13.080s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 104.690s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 453.020s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 60545705937621085021949632997566497803482489078181418503929644530725583562915 98
UVM_ERROR @ 24368182 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 24368182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 40545664977603600588171603190120655372256194245880869747688600313735379015672 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 126044137 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 126044137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 100205632941709456245828302094034884780085360270167788416488055671538734813444 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 64131948 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 64131948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 113104228406329319460667715279205460404481531345006203964101212926664183031368 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 118403462 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 118403462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 13984835500595933446552551209926238310644574318892515595566063275586001930365 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 86812136 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 86812136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 75931422520143287871426734217469804195620017728757129301805706569526009969126 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 66566271 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 66566271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 60299507987390226679656338202379118966892041319632003787045709435875511791368 103
UVM_ERROR @ 9212797 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9212797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 99262874110288199360409615239674435008197720265856249623833758545898961809248 100
UVM_ERROR @ 3267314 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3267314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 10640624887461937997245468308642624647229653238884984061382350404508258808648 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 5968144 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5968144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 17939588909881380408785326578788169591092394239934579161509774888469527461991 98
UVM_ERROR @ 86650974 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x5c)
UVM_INFO @ 86650974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 90112857675522675522183145025322663104196187296099161389998809228306215462957 98
UVM_ERROR @ 51604369 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x55)
UVM_INFO @ 51604369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 29704524446489336472321178420911285026322426815495436920844893406240031150987 98
UVM_ERROR @ 27255499 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0xe)
UVM_INFO @ 27255499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 108418216945531422980078881139987439387136543072619366602299422402200377560365 98
UVM_ERROR @ 51057926 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x48)
UVM_INFO @ 51057926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 80489118665348671013412197391308990994967025667748236334752057951603824064105 98
UVM_ERROR @ 29277800 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x4e)
UVM_INFO @ 29277800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 7288789862415978343357630027660265293037277112479002653633914046520316914990 98
UVM_ERROR @ 27798641 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5e) != exp (0x55)
UVM_INFO @ 27798641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 81216961633610399822323138035546956676469348655871310477957948972816822047436 98
UVM_ERROR @ 68536097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x11) != exp (0x38)
UVM_INFO @ 68536097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 38146332486638248497703462238379776401269841090327659462809547408017526677229 98
UVM_ERROR @ 115577774 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x16)
UVM_INFO @ 115577774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 82172291413789941249030962852315870355047461154669488625340589298967868024513 98
UVM_ERROR @ 92268647 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x20)
UVM_INFO @ 92268647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 68510750312709871520980447747884958645587218995033947864376452429811523653977 98
UVM_ERROR @ 90970137 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x27)
UVM_INFO @ 90970137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 96206184303233822160072595974196970471164003562234645542897454429229516407277 98
UVM_ERROR @ 395113174 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x3f)
UVM_INFO @ 395113174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54482317485944774371350738187791233102308266328390673029816487715578611889356 98
UVM_ERROR @ 269629551 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x76)
UVM_INFO @ 269629551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12777828082105372129539815047541715253609841164963663615245179313241894658658 98
UVM_ERROR @ 38302775 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x63) != exp (0x13)
UVM_INFO @ 38302775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 104821450791066243799755975795984471310279723396327826623279473742121039908383 98
UVM_ERROR @ 29998938 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x69)
UVM_INFO @ 29998938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 92767407290655295071041493498704062655436855815671443890005184925445447267591 100
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1526854ps failed at 1526854ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 1537271ps failed at 1537271ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 36543984085002586122397035571128424495256292831978634383288002247653843141392 101
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3469843ps failed at 3469843ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 6615702 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6615702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire
sram_ctrl_readback_err 75289876952814667394921121827795167459098059496049171173076608110291222745040 98
UVM_ERROR @ 27093044 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire
UVM_INFO @ 27093044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---