Simulation Results: alert_handler

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.05 %
  • code
  • 98.92 %
  • assert
  • 98.88 %
  • func
  • 99.36 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.51 %
  • toggle
  • 97.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.03%
V2S
99.55%
V3
66.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 9.750s 0.000us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 10.500s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 426.910s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 180.030s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 15.660s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 10.500s 0.000us 20 20 100.00
alert_handler_csr_aliasing 180.030s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 364.580s 0.000us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 68.580s 0.000us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 2607.130s 0.000us 50 50 100.00
sig_int_fail 50 50 100.00
alert_handler_sig_int_fail 53.920s 0.000us 50 50 100.00
clk_skew 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 75.190s 0.000us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 59.040s 0.000us 50 50 100.00
ping_timeout 24 50 48.00
alert_handler_ping_timeout 461.400s 0.000us 24 50 48.00
lpg 95 100 95.00
alert_handler_lpg 2353.410s 0.000us 47 50 94.00
alert_handler_lpg_stub_clk 2882.410s 0.000us 48 50 96.00
stress_all 50 50 100.00
alert_handler_stress_all 3960.920s 0.000us 50 50 100.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 42.150s 0.000us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 4.650s 0.000us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.450s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 24.480s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 24.480s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 9.750s 0.000us 5 5 100.00
alert_handler_csr_rw 10.500s 0.000us 20 20 100.00
alert_handler_csr_aliasing 180.030s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 39.850s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 9.750s 0.000us 5 5 100.00
alert_handler_csr_rw 10.500s 0.000us 20 20 100.00
alert_handler_csr_aliasing 180.030s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 39.850s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 298.160s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 298.160s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 298.160s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 298.160s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 967.310s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_tl_intg_err 62.210s 0.000us 20 20 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 62.210s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 298.160s 0.000us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 78.300s 0.000us 50 50 100.00
sec_cm_alert_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 53.920s 0.000us 50 50 100.00
sec_cm_lpg_intersig_mubi 47 50 94.00
alert_handler_lpg 2353.410s 0.000us 47 50 94.00
sec_cm_esc_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 53.920s 0.000us 50 50 100.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2607.130s 0.000us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2607.130s 0.000us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 45.880s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 33 50 66.00
alert_handler_stress_all_with_rand_reset 428.430s 0.000us 33 50 66.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 37390657787219179379659751921401879280023514446699956858350302942058455992787 98
UVM_ERROR @ 5771788328 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 5771788328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 50490507683223238493036651539818542884198146301043357335600629624546288138976 84
UVM_ERROR @ 2639820422 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 2639820422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 1038665213429981441650558522988755301408361320845668375609186448723621290486 84
UVM_ERROR @ 7900114839 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 7900114839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 98608622888363517151068341916808950375109101217513943881023050556635415468856 105
UVM_ERROR @ 5031599407 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 5031599407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 33342589076142324865660607166832045482125612394941384990575346765357700802955 87
UVM_ERROR @ 1178517844 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 1178517844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 18244435820177413273746377411957772155359153292552231492879043643458948825487 126
UVM_ERROR @ 28309089528 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 28309089528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 53759904635323805818568545526725730589690572221642926359599685454164220188270 87
UVM_ERROR @ 3567543063 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 3567543063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 48974421649947010310007488381999567271913506240123573406227415032173225187263 118
UVM_ERROR @ 5571723643 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 5571723643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 20828577749251640448049346624902188001640077823061538361982839835207247672624 97
UVM_ERROR @ 10619700370 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 10619700370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 104740259637006701015298793831898318457104436315776506724045153781675885449231 81
UVM_ERROR @ 23097081672 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 23097081672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 89852027548903046744821938607079959837254443641117931082064339706615188231142 87
UVM_ERROR @ 2407700198 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2407700198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 98395313284520473814326730027250342183634362374923405993019333975725955863860 114
UVM_ERROR @ 21053906982 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 21053906982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 12688738035289276744536128851149026140427788411195465190119281680240603045915 90
UVM_ERROR @ 2862963927 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 2862963927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 53774474969811257917000350684488202184394993062313178152282954075681135295072 110
UVM_ERROR @ 6329568331 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 6329568331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 82556447164265458115222739365027821959109511723800299887086239712478380545009 123
UVM_ERROR @ 5378950399 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 5378950399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 115251932547061821406425819132511648273364038733836692759134927122300706311891 102
UVM_ERROR @ 17060476057 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 17060476057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 13234555820650186151358710423139155424572681210072419023195797950298963761543 87
UVM_ERROR @ 1792695017 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 1792695017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 44678543956393966567015468208478557220457781210651423490385608147776451557034 93
UVM_ERROR @ 5842245676 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 5842245676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 83564221302207921934562633478339048974560300657311084553432256827197875448839 80
UVM_ERROR @ 18202730813 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 18202730813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 79483721143372062573290777057314041338594883773102138777896953484184045176453 93
UVM_ERROR @ 9500259312 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 9500259312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 21966163125808557020314110561892884941307966907556393380826126539695726527073 90
UVM_ERROR @ 9582472152 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 9582472152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 51064836744347856192362905711601011451124985394437506414139117068296740504252 96
UVM_ERROR @ 4263541985 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4263541985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 38536552141227161740618618242349836992509743019918697204070064630556168367665 144
UVM_ERROR @ 7816492902 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 7816492902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 110541095760818917446199846555585533051569857662918020202771345865374131490192 144
UVM_ERROR @ 10650204030 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 10650204030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 106926972281646127199168030221352806798578501636373281158039573478713299761803 126
UVM_ERROR @ 49943321511 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 49943321511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 105673894137933172546076762861768670468357891711782681678941472591072298807116 115
UVM_ERROR @ 15252812192 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15252812192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 27333911061470137653669956595884797373040646587011481663058819812740386862075 107
UVM_ERROR @ 155865120 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 155865120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 609906257474338018707325332498511808742713521897473763091513975559580717992 82
UVM_ERROR @ 534821385 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 534821385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 86451975304400102830746709267063447541447724277311098943066621972003677534644 119
UVM_ERROR @ 21018181072 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21018181072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 49449265307307637849476806308638165501146860009518978316261995946714532051507 84
UVM_ERROR @ 210826643 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 210826643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 83918675398366828443429574391446609621347233104203187259441696166497560397623 100
UVM_ERROR @ 152417205 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 152417205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 31890997353151087334813683205574748931605801776064326061217777516851328964611 111
UVM_ERROR @ 792278536 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 792278536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 104910276037750485319172052408533425602248417037488046521903598610795397296463 93
UVM_ERROR @ 168008527 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 168008527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 26826501825763849424183416359044158220361142259867217296385371382460263034710 93
UVM_ERROR @ 811430360 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 811430360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 81807630203096615821844781689229982431908865682030910684465957358296915285436 92
UVM_ERROR @ 193964770 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10058 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 193964770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 89304524002108830640061758914193148768223819833999197332549735638212724237531 164
UVM_ERROR @ 11307564332 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11307564332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 5508193146445616834976674960538748301739668490436911144388713841854401388347 152
UVM_ERROR @ 11905413493 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11905413493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 25347374921457519671076471996129524279889113367050843893032535903751435508849 84
UVM_ERROR @ 391477204 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 391477204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 77138262461908778748599356479269697842098097347811901133692871399116576833381 141
UVM_ERROR @ 7894286792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7894286792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 84775504802491406040874867127389690401376274183855834841185341189370000977839 178
UVM_ERROR @ 12118332295 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12118332295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 93187460849900561278389267826099712753881513132849572843876134650055092513954 94
UVM_ERROR @ 260808975 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 260808975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:598) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 34779662294747137706175412887928271677927880607299272758830993157738641709107 80
UVM_ERROR @ 496882784 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 496882784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 5639936219506253215561441376450997074626128596030894835310362394771744701170 80
UVM_ERROR @ 27514812477 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 27514812477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 32451918115267391826130364940693803317574699763675461652085287370826449320573 80
UVM_ERROR @ 3456216906 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3456216906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 43605520468501769200454558341589928487925678641247353151199767206886169298998 80
UVM_ERROR @ 381133427 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 381133427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt
alert_handler_lpg_stub_clk 57508273667810353599010721099294397648285521903677423937239445579573512516440 80
UVM_ERROR @ 36635505753 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1145 [0x479] vs 1146 [0x47a]) reg name: alert_handler_reg_block.classa_accum_cnt
UVM_INFO @ 36635505753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 210924872524464244751012778523719542145974572740874605629776417148783056993 126
UVM_ERROR @ 2765374061 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2765374061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail)
alert_handler_lpg_stub_clk 68626786730858133877835416744496925261152593825634174642463644006788951155116 81
UVM_ERROR @ 61025179471 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[1]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalAlertPingFail)
UVM_INFO @ 61025179471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---