Simulation Results: clkmgr

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.43 %
  • code
  • 98.99 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.38 %
  • branch
  • 99.26 %
  • cond
  • 96.31 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.44%
V3
99.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.570s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.240s 0.000us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 14.320s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.660s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.180s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.660s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.230s 0.000us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.670s 0.000us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.410s 0.000us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.280s 0.000us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.570s 0.000us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 13.690s 0.000us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 12.320s 0.000us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 13.690s 0.000us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 56.220s 0.000us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.790s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 3.440s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 3.440s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.240s 0.000us 5 5 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.660s 0.000us 5 5 100.00
clkmgr_same_csr_outstanding 1.990s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.240s 0.000us 5 5 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
clkmgr_csr_aliasing 1.660s 0.000us 5 5 100.00
clkmgr_same_csr_outstanding 1.990s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 22 25 88.00
clkmgr_sec_cm 2.870s 0.000us 2 5 40.00
clkmgr_tl_intg_err 2.980s 0.000us 20 20 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 5.510s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 5.510s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 5.510s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 5.510s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 16 20 80.00
clkmgr_shadow_reg_errors_with_csr_rw 4.410s 0.000us 16 20 80.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 2.980s 0.000us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 13.690s 0.000us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 12.320s 0.000us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 5.510s 0.000us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.600s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.560s 0.000us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.500s 0.000us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 48 50 96.00
clkmgr_clk_handshake_intersig_mubi 1.590s 0.000us 48 50 96.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.710s 0.000us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
sec_cm_idle_ctr_redun 2 5 40.00
clkmgr_sec_cm 2.870s 0.000us 2 5 40.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.260s 0.000us 20 20 100.00
prim_count_check 2 5 40.00
clkmgr_sec_cm 2.870s 0.000us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 7.320s 0.000us 50 50 100.00
stress_all_with_rand_reset 49 50 98.00
clkmgr_stress_all_with_rand_reset 153.880s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 76321990772338938611162562928334040917351475516611803660258777926393915380523 81
UVM_ERROR @ 6425010 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 6425010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 10835823920366785697415407460963875930055882834651406320341528693343319226846 81
UVM_ERROR @ 8350054 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 8350054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 2822467397839654477067940323947476945710708479395581838520437490482187709597 77
UVM_ERROR @ 2169431 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 2169431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
clkmgr_stress_all_with_rand_reset 53410748043735792155288982148613748595068366109583930420747519795336238640323 305
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
UVM_ERROR @ 4220059845 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
UVM_INFO @ 4220059845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 93210599209391042455423781232745961092770229854818528747890577376721703976818 74
UVM_ERROR @ 7085626 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (13 [0xd] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 7085626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 72910075178801979621310478108800186658875141313032596609647643347411719514629 74
UVM_ERROR @ 6391302 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (5 [0x5] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 6391302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status
clkmgr_shadow_reg_errors_with_csr_rw 38468065248147737417314536313093621347475352339186686020961592757617479546092 75
UVM_ERROR @ 57540140 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: 0x0 Write_and_check_update_error task: check storage_err status
UVM_INFO @ 57540140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 22336530880067339904147983378231718813209981829862246042596308882133819083151 75
UVM_ERROR @ 51585403 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 51585403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 115426399068557167376357395481808130371471933457850787701302860497636873457745 76
UVM_ERROR @ 167088015 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 167088015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 72649805551015424118941230836397917252615982156063439155827525016247765504780 75
UVM_ERROR @ 85146325 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 85146325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---