Simulation Results: edn/edn0

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.51 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
99.51%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.460s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.330s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.310s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 6.600s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.990s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.170s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.310s 0.000us 20 20 100.00
edn_csr_aliasing 1.990s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 105.970s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 105.970s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 105.970s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.650s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 2.160s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 0.000us 100 100 100.00
disable 92 100 92.00
edn_disable 1.370s 0.000us 50 50 100.00
edn_disable_auto_req_mode 20.630s 0.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 7.850s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.330s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.420s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.450s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.450s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.330s 0.000us 5 5 100.00
edn_csr_rw 1.310s 0.000us 20 20 100.00
edn_csr_aliasing 1.990s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.780s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.330s 0.000us 5 5 100.00
edn_csr_rw 1.310s 0.000us 20 20 100.00
edn_csr_aliasing 1.990s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.780s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 4.100s 0.000us 20 20 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.450s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.160s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.160s 0.000us 200 200 100.00
edn_sec_cm 8.150s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.160s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.100s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 125.290s 0.000us 44 50 88.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 93241646053468956498513943512852693958178013774923079665166251713181282953926 240
UVM_ERROR @ 611182357 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 611182357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 78152587447441877265112639767714380528347931137288137583181968348858182713786 110
UVM_ERROR @ 120458910 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120458910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 86892924155755693479856453723441781607928189146331135565835254977245055765075 294
UVM_ERROR @ 2645567602 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2645567602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 109584469570536915398608667189811653575923929412714441908839626149006040207126 301
UVM_ERROR @ 1335084476 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1335084476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 14040688741778903275975772377203119922335566925691886721292663668342820082685 201
UVM_ERROR @ 1363426247 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1363426247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35406441720457422935281581144626406639815642747189117984005405428637814545265 195
UVM_ERROR @ 2347382344 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2347382344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 72670994141450508948571306554734843267681757667681998993608142030796074001946 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 64847882304463544346211485255138710072854914827162631136410058985355116187684 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 50294949404026901429031613489564864283047234882755088126339195850116187192916 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 74598659501244536421283769656407946910484758490039562424330776640701822973954 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 40603882137180649854156287662931834447657928111695581960531118566248262576777 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 54518647625351297488059798070491803727815965075425825965400174679069792397999 88
UVM_FATAL @ 21462217 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00c7e642 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 21462217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 15059113273222174346182616164838430107780052689232020468818968705409996541838 88
UVM_FATAL @ 10410796 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003f2912 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 10410796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 52936126777570013637847674561182068528100783437984775101816211673872150891374 88
UVM_FATAL @ 56684813 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0044d642 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 56684813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---