Simulation Results: edn/edn1

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 96.41 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.63%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.360s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.960s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.950s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.850s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.250s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.950s 0.000us 20 20 100.00
edn_csr_aliasing 1.250s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 187.400s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 187.400s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 187.400s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.570s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.570s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.520s 0.000us 100 100 100.00
disable 94 100 94.00
edn_disable 1.230s 0.000us 50 50 100.00
edn_disable_auto_req_mode 9.420s 0.000us 44 50 88.00
stress_all 50 50 100.00
edn_stress_all 5.430s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.840s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.430s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.830s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.830s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.960s 0.000us 5 5 100.00
edn_csr_rw 0.950s 0.000us 20 20 100.00
edn_csr_aliasing 1.250s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.090s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.960s 0.000us 5 5 100.00
edn_csr_rw 0.950s 0.000us 20 20 100.00
edn_csr_aliasing 1.250s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.090s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
edn_tl_intg_err 3.440s 0.000us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.350s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.570s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.570s 0.000us 200 200 100.00
edn_sec_cm 4.980s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.570s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.440s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 90.060s 0.000us 44 50 88.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 80252764464002690182002024347936894047623568136889986944613690690942538509737 139
UVM_ERROR @ 678009381 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 678009381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 12240105412925780999186272313985423747322714966844872458772399210231825565476 290
UVM_ERROR @ 2623775557 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2623775557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 811455984606568125402878108144321750802551585801992001091833607525728355197 207
UVM_ERROR @ 1257132074 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1257132074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 44402758747193796497165236606407889124986393709419954775021897262704772999438 162
UVM_ERROR @ 1240863982 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1240863982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70686742930897393717408119211652546452555477487373591553214860536946005360665 294
UVM_ERROR @ 3005592453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3005592453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 58511044757389631856582211749513133614053414147890966178978137773584905705150 194
UVM_ERROR @ 2051480902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2051480902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 24354891728464805218584264216594829871175921432712254631532225665227401997105 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 113346138549891876288045352340702256786164402457747345573163308471637202316792 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 55119778902985454307606575618643652218549332164404269070882195943354041863886 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 8257289598410190925821482577559292330729383394468611786545642921058282238969 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43858260127398057065372360475322617612971622126945264209910474766780276787234 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 98019067607290665767731831234381393845324390744378370350853680976503714318159 88
UVM_FATAL @ 33160076 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f0e902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 33160076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---