Simulation Results: keymgr

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 98.91 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.16 %
  • toggle
  • 98.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.93%
V2S
99.22%
V3
56.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 22.460s 0.000us 50 50 100.00
random 50 50 100.00
keymgr_random 28.330s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.400s 0.000us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 23.790s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 7.450s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.490s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_csr_aliasing 7.450s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 77.170s 0.000us 50 50 100.00
sideload 199 200 99.50
keymgr_sideload 53.680s 0.000us 50 50 100.00
keymgr_sideload_kmac 36.220s 0.000us 50 50 100.00
keymgr_sideload_aes 43.640s 0.000us 49 50 98.00
keymgr_sideload_otbn 23.990s 0.000us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 11.890s 0.000us 50 50 100.00
lc_disable 47 50 94.00
keymgr_lc_disable 4.380s 0.000us 47 50 94.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 5.150s 0.000us 49 50 98.00
invalid_sw_input 49 50 98.00
keymgr_sw_invalid_input 45.930s 0.000us 49 50 98.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 23.440s 0.000us 49 50 98.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 11.340s 0.000us 50 50 100.00
stress_all 48 50 96.00
keymgr_stress_all 186.910s 0.000us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.270s 0.000us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.370s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 5.110s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 5.110s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.400s 0.000us 5 5 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_csr_aliasing 7.450s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 4.350s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.400s 0.000us 5 5 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_csr_aliasing 7.450s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 4.350s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 12.010s 0.000us 20 20 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.200s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.200s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.200s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.200s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.840s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 12.010s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.200s 0.000us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 77.170s 0.000us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_random 28.330s 0.000us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_random 28.330s 0.000us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.660s 0.000us 20 20 100.00
keymgr_random 28.330s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 47 50 94.00
keymgr_lc_disable 4.380s 0.000us 47 50 94.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 23.440s 0.000us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 23.440s 0.000us 49 50 98.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 28.330s 0.000us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 12.090s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 27.380s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 47 50 94.00
keymgr_lc_disable 4.380s 0.000us 47 50 94.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.380s 0.000us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.380s 0.000us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.380s 0.000us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.050s 0.000us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 27.380s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 50 56.00
keymgr_stress_all_with_rand_reset 18.930s 0.000us 28 50 56.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 104205081418619230367366663478970289270247082752082595651802010804659302957073 215
UVM_ERROR @ 2661662866 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2661662866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65145642679837769152622018770347284657982832710388514126641991198301763521814 573
UVM_ERROR @ 178963582 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 178963582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25259733040257410009525308823555867577774918985812114380544800244040083021951 297
UVM_ERROR @ 243744042 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 243744042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26395938426803665058280071139081303394830133071308313241628986187882081135178 117
UVM_ERROR @ 482007799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 482007799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23570595176125410275468308785763880517480082146676950955555388089020213477142 102
UVM_ERROR @ 470128054 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 470128054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 14739290683819194401611114466415051080782417466367488304212169935184382122334 1919
UVM_ERROR @ 1564397952 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1564397952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 66216421964216131333951525657652011122487396231666738550108717326762586998943 484
UVM_ERROR @ 1125550306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1125550306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 67140843578159760186078741121487588252095697158287223366987114146917015255703 360
UVM_ERROR @ 703643758 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 703643758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50077781306971534254910261674325435966225667207017774726573408232534891080672 673
UVM_ERROR @ 232380601 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 232380601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56368429534147651641871724404229615640995772577683460566108968236916659528020 97
UVM_ERROR @ 220011005 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 220011005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 34067916302098139090668966662190556125556764650765041028582841004309455935665 163
UVM_ERROR @ 425137556 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 425137556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 34240588277936502607956153523151806530959457914036395210074435088828554384533 756
UVM_ERROR @ 807481610 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 807481610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83676585086099423699015242644668793923171736927983636112646134505438986051943 625
UVM_ERROR @ 530163502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 530163502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 70214746752801856645732499541012355719033192755715539613510221650501701215218 824
UVM_ERROR @ 1094644602 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1094644602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 55874968257100642998379624090890321144527163703552344952693560598847369427618 434
UVM_ERROR @ 125097598 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 125097598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 5925313425273726946024694955051328176683197208865877442993352492776719916735 483
UVM_ERROR @ 357823954 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 357823954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 66729383987370148176737665502213210573093345385925692039882544714580790889924 913
UVM_ERROR @ 520578811 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 520578811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 3579653277633972072501322551981253027688734976063707565294915517253757818611 622
UVM_ERROR @ 433579061 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 433579061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 33403369329370198223257698343324050790251186230013400741490099806774204694243 618
UVM_ERROR @ 183717719 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 183717719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79864404305568418161170869082520483359612701725722471242209729442065853877384 167
UVM_ERROR @ 136083775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 136083775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 3472259785187587705156311291354846263814626009018426553295212456878397184586 524
UVM_ERROR @ 1769751469 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1769751469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 23097333708778264651463577056362065346568541616075448513207813175487368578317 831
UVM_ERROR @ 2520226507 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2520226507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 24420898202197614337771852331684318668266126353360182156776869002064717132627 146
UVM_ERROR @ 73045188 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 73045188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload_aes 70143965824463079292151684835024137222638393426135776752742659276240001428792 113
UVM_ERROR @ 4347837 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 4347837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sw_invalid_input 69389108553559692870409700218883591298972082067270604551600717558649824335413 279
UVM_ERROR @ 42037836 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 42037836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_kmac_rsp_err 53388600918005561745652524654101336364500737190985515288114364386198389025686 97
UVM_ERROR @ 4214873 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 4214873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all 71687257080844382926256288336432456082666499246688000741157476141476720044401 1902
UVM_ERROR @ 543790895 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1171513521 [0x45d3e0b1] vs 1171513521 [0x45d3e0b1]) reg name: keymgr_reg_block.sw_share0_output_1
UVM_INFO @ 543790895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 105092025742235667374721497744598026606185190459978462370246987992990761976175 128
UVM_ERROR @ 17528015 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 17528015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
keymgr_hwsw_invalid_input 17081139134117239820314944706718566594856856845327025770180794493944870401571 339
UVM_ERROR @ 133543605 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 133543605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
keymgr_lc_disable 25875363747611521497013195124201124061815503686368248596389124882216874150451 233
UVM_ERROR @ 225426466 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
UVM_INFO @ 225426466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
keymgr_stress_all_with_rand_reset 47259792194577839818683817275822186977714344844761875803077238548786159647286 718
UVM_ERROR @ 239212777 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 239212777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---