Simulation Results: kmac/unmasked

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 92.55 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.79 %
  • toggle
  • 100.00 %
  • FSM
  • 74.38 %
Validation stages
V1
100.00%
V2
98.21%
V2S
99.80%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 59.210s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.270s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.570s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.290s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.280s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.990s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.570s 0.000us 20 20 100.00
kmac_csr_aliasing 7.280s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.160s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.620s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3017.850s 0.000us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 964.870s 0.000us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1913.500s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 1891.050s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 1265.520s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 929.110s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 2168.070s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 1917.870s 0.000us 5 5 100.00
kmac_test_vectors_kmac 2.450s 0.000us 5 5 100.00
kmac_test_vectors_kmac_xof 2.120s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 430.030s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 309.810s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 282.240s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 294.400s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 421.000s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.270s 0.000us 50 50 100.00
sideload_invalid 35 50 70.00
kmac_sideload_invalid 144.030s 0.000us 35 50 70.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 37.570s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 43.460s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 63.680s 0.000us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 35.150s 0.000us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2174.500s 0.000us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.200s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.300s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.070s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.070s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.270s 0.000us 5 5 100.00
kmac_csr_rw 1.570s 0.000us 20 20 100.00
kmac_csr_aliasing 7.280s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.520s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.270s 0.000us 5 5 100.00
kmac_csr_rw 1.570s 0.000us 20 20 100.00
kmac_csr_aliasing 7.280s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.520s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.130s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.130s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.130s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.130s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 4.120s 0.000us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 55.060s 0.000us 5 5 100.00
kmac_tl_intg_err 6.000s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.000s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 35.150s 0.000us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 59.210s 0.000us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 430.030s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.130s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 55.060s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 55.060s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 55.060s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 59.210s 0.000us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 35.150s 0.000us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 55.060s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 326.240s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 59.210s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 159.860s 0.000us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 9046086316507155405275988249654310862872343455746626028749446545332129699589 253
UVM_ERROR @ 3100950963 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3100950963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27)
kmac_sideload_invalid 110305092838066137721330116647135004271018692410392429744964437596009026367792 107
UVM_FATAL @ 10572115519 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3d1f4000, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10572115519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 29688567662399770221339420294271730074904533574382372406766135320406548098499 225
UVM_ERROR @ 3897780051 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3897780051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 25250787994413659896283354056443351026980040196155166655545778468129378871410 245
UVM_ERROR @ 20042693063 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20042693063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 76631666214451787088349724488113365045860530977307676340838669827968930700226 84
UVM_FATAL @ 10090892094 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x48e44000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10090892094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 95413821582208484049554001313558817901631467085892349944838748586087456276582 83
UVM_FATAL @ 10050271690 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2cacf000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10050271690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 40880967860272121307117644052453318788201259463509468455412521253444970613803 84
UVM_FATAL @ 10037601025 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe67bd000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10037601025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 51634532141338612558913443865429829086101336678839630185726256239896549391708 80
UVM_FATAL @ 10140832374 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaa62c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10140832374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 89310540921956600121080775510858853304800864216453759564408453420914576646883 84
UVM_FATAL @ 10040550488 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x21b55000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10040550488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 87740381287622703551960726002173106158093146771864998877591706994736024145257 85
UVM_FATAL @ 10093065990 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x82c57000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10093065990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 55581366204259158300331120764567442040443880287138670552424774121103226468945 86
UVM_FATAL @ 10065763347 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf903a000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10065763347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 103351876809424665627619419026749884306675857206375839962177191910212181465638 88
UVM_FATAL @ 10180822106 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa1bfa000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10180822106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26)
kmac_sideload_invalid 96640571324394288196867178298492480373844245952128206751701939371965300932623 104
UVM_FATAL @ 10156660675 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfb572000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10156660675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 71350843046601820318078735024152355118389824642923822648539174852157095811223 81
UVM_FATAL @ 10024778565 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x11b79000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10024778565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 73312845724879841140207566739690848412919367999905193851523099688490536882767 81
UVM_FATAL @ 10027619002 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x657d9000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10027619002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)
kmac_sideload_invalid 83876496933253873745887679817305295077541792268077516974590154897027188214203 100
UVM_FATAL @ 10391637671 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c430000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10391637671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 5412585416723756339542749219630688589795049775024500824097223340327370251785 79
UVM_FATAL @ 10094256649 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa6971000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10094256649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 19855528436475346320430188638790083805991880167929216156063280901876604593373 78
UVM_FATAL @ 10015946925 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x54d3d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10015946925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 52609485812779652268403700627384086165068260690321076128405476408735470370184 181
UVM_ERROR @ 77809098 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (816376795 [0x30a8ebdb] vs 0 [0x0]) Regname: kmac_reg_block.prefix_0 reset value: 0x0
UVM_INFO @ 77809098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---