Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.29 %
  • code
  • 86.17 %
  • assert
  • 94.27 %
  • func
  • 96.44 %
  • line
  • 97.26 %
  • branch
  • 94.27 %
  • cond
  • 81.57 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.09%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.020s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.570s 0.000us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.390s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.650s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.760s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.520s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.390s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 10.410s 0.000us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.640s 0.000us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.340s 0.000us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 6.420s 0.000us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 13.660s 0.000us 49 50 98.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_prog_failure 6.420s 0.000us 50 50 100.00
lc_ctrl_errors 13.660s 0.000us 49 50 98.00
lc_ctrl_security_escalation 15.410s 0.000us 50 50 100.00
lc_ctrl_jtag_state_failure 81.290s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.460s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 93.570s 0.000us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_csr_hw_reset 3.280s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.980s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 19.630s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.160s 0.000us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.050s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.290s 0.000us 10 10 100.00
lc_ctrl_jtag_alert_test 2.420s 0.000us 10 10 100.00
lc_ctrl_jtag_smoke 10.710s 0.000us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.530s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.460s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 93.570s 0.000us 18 20 90.00
lc_ctrl_jtag_access 24.350s 0.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 24.580s 0.000us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 34.500s 0.000us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.610s 0.000us 50 50 100.00
stress_all 47 50 94.00
lc_ctrl_stress_all 507.350s 0.000us 47 50 94.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.940s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.250s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.250s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.570s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.390s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.580s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.570s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.390s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.580s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.020s 0.000us 20 20 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.020s 0.000us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.640s 0.000us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.140s 0.000us 50 50 100.00
lc_ctrl_sec_cm 12.370s 0.000us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 15.410s 0.000us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 10.410s 0.000us 50 50 100.00
lc_ctrl_jtag_state_post_trans 24.530s 0.000us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 28.860s 0.000us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 28.860s 0.000us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.040s 0.000us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.710s 0.000us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.710s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 50 50.00
lc_ctrl_stress_all_with_rand_reset 150.630s 0.000us 25 50 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 61440729200913745011428919581850940047972018949202503468121604038269151028353 1984
UVM_ERROR @ 2368510582 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2368510582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24291598877824862438884526023545659665051512194210182322044257660264021327402 150
UVM_ERROR @ 435596009 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 435596009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86191587646733323052171312321878220832448618678836539868842024656247760347640 952
UVM_ERROR @ 1615731558 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1615731558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104094731375679129740082377130922902608590185281644624724477890275755803003256 12577
UVM_ERROR @ 4846179533 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4846179533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75968687804865819023806291770859669442747383450418341931423291368750380982447 6108
UVM_ERROR @ 2690990647 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2690990647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27610778779255388995354044060905773459057373284279580225352268507529347672130 8703
UVM_ERROR @ 4973311714 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4973311714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84764403874137208566154402742188076167673074252151489580567462039637571012773 7534
UVM_ERROR @ 5245529103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5245529103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42564368024505213541763872262215570353433842725055082312695415687193396083346 3148
UVM_ERROR @ 1070649234 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1070649234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38355483497571290219632976115301712061018453408178834168443524421814700785 2018
UVM_ERROR @ 2047543541 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2047543541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66909079501021198538268442926968497131117320585865943152906670748230639486824 652
UVM_ERROR @ 1421980067 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1421980067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60985735714874181043559664236798747247685360584257139925543450997522079593213 1334
UVM_ERROR @ 16852479638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16852479638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70218022990560171357521165650839679833349834816608945080912312613488034499653 1102
UVM_ERROR @ 596833712 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 596833712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37439537827689303592633885304883343518995237909776247938602634037490761208855 5329
UVM_ERROR @ 3437710179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3437710179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96220471366275482757438967134503142717165502945271418113887779527316723395304 11108
UVM_ERROR @ 13282143116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13282143116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25511038650980155497150690747007455220420508353282134656311940109856769716116 3326
UVM_ERROR @ 5395179648 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5395179648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103663195731429629026132570130216125127489594063080289620571211882312609390111 4496
UVM_ERROR @ 1491907662 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1491907662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79609467790837996007224301646450844492296975480779370565604415491526979003971 8729
UVM_ERROR @ 4981803897 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4981803897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85318936074029133449050935478377765003246931783704305217813721830000838513826 1215
UVM_ERROR @ 973856021 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 973856021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75167403001270295166121857390861554237771654584310272788007570575591449642360 9657
UVM_ERROR @ 989578755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 989578755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44160652162937704850701232365864744566921735228954364263881070816147352680790 321
UVM_ERROR @ 481701301 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 481701301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50173701957478404257305111747580910148723672252109927768089401766562989635490 1000
UVM_ERROR @ 1032527542 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1032527542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57475203165788475806753557815867923544955639799681884732570631566839569686145 482
UVM_ERROR @ 21771302460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21771302460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42690488475134311148950554384009426294383596576966535673120826254084272631872 175
UVM_ERROR @ 2761907757 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2761907757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 109676816266691861683139723893686289343472227827020908018533413661249790889918 2354
UVM_ERROR @ 1914659589 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1914659589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 76452161820136798246110299504433462285497962568893369682268199365303700128316 422
UVM_ERROR @ 728959761 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 728959761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 86925325252757128876790088760467168044860885316962756573704817825326458346474 2543
UVM_ERROR @ 5035229585 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5035229585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19258289496373612687615414039345104541133938493326711260750142873302898535885 3102
UVM_ERROR @ 819412522 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 819412522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 54675520342449702406698295032596582725929783279293068834926298670325904775854 332
UVM_ERROR @ 73612438 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 73612438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 90453459956037193656959310484584748013341622912735964237335377897212225664066 1485
UVM_ERROR @ 753085119 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 753085119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 24425978109848710929770107337561147873060655157434903017108665686068742683174 958
UVM_ERROR @ 148566875 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 148566875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*
lc_ctrl_stress_all_with_rand_reset 7198217763334739193800061064351402495756254249551986206410739131464087231651 1321
UVM_ERROR @ 8600191868 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked3
UVM_INFO @ 8600191868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---