Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.28 %
  • code
  • 86.46 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.24 %
  • branch
  • 94.36 %
  • cond
  • 81.98 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.49%
V2S
100.00%
V3
38.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 8.200s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.280s 0.000us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.460s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.540s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 2.010s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.420s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.460s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 2.010s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.780s 0.000us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 24.810s 0.000us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.330s 0.000us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.090s 0.000us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 16.440s 0.000us 49 50 98.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_prog_failure 4.090s 0.000us 50 50 100.00
lc_ctrl_errors 16.440s 0.000us 49 50 98.00
lc_ctrl_security_escalation 12.160s 0.000us 50 50 100.00
lc_ctrl_jtag_state_failure 48.580s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 17.190s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 93.590s 0.000us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 11.810s 0.000us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.710s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 17.190s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 93.590s 0.000us 19 20 95.00
lc_ctrl_jtag_access 18.220s 0.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 29.310s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 6.160s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.570s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.740s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.430s 0.000us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.340s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.370s 0.000us 10 10 100.00
lc_ctrl_jtag_alert_test 2.640s 0.000us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 23.470s 0.000us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.680s 0.000us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 372.480s 0.000us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.700s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.710s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.710s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.280s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.460s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 2.010s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.050s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.280s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.460s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 2.010s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.050s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
lc_ctrl_tl_intg_err 4.610s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.610s 0.000us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 24.810s 0.000us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.060s 0.000us 50 50 100.00
lc_ctrl_sec_cm 9.950s 0.000us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.160s 0.000us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.780s 0.000us 50 50 100.00
lc_ctrl_jtag_state_post_trans 21.710s 0.000us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 25.740s 0.000us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 25.740s 0.000us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 21.910s 0.000us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 17.320s 0.000us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 17.320s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 50 38.00
lc_ctrl_stress_all_with_rand_reset 140.140s 0.000us 19 50 38.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 75447066091213035133019691917324798419185759981185710552366224713978538456698 2419
UVM_ERROR @ 13763546147 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13763546147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 2883168406090046154953322066018584426486358857506129690290569986101807257675 20215
UVM_ERROR @ 3315281288 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3315281288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 11155963235386950273930143205360624545359970700532494661561619253651537726115 2397
UVM_ERROR @ 153058126 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 153058126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6236851050566407216029791347136284234062679711992921216701827527289280090133 1390
UVM_ERROR @ 934091107 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 934091107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 97524426413895842529771454258798540932294348052955071861199462998118483840412 1596
UVM_ERROR @ 2880111823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2880111823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66297264053894658074559686762950463992382635305021827383619880466728775151826 3716
UVM_ERROR @ 8116547784 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8116547784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6527190357857978487800568919197334534542360467149138692117510074816014214201 2643
UVM_ERROR @ 2956022884 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2956022884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75728931065687276653402821814716777233336051872673362283879583373828113656734 450
UVM_ERROR @ 6270332826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6270332826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65461480044875653031327349300788488411876924498151135407689768606633707628773 2178
UVM_ERROR @ 2120848669 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2120848669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58862219332320532148519161212727964870680708557212350131773326434354499814868 150
UVM_ERROR @ 645800922 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 645800922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13327151450622244920239003697493082214311364478727418176104497875828013481635 6112
UVM_ERROR @ 18703711932 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18703711932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 4208185595929099088809307869270307543849756809865724044321147301119192721899 4173
UVM_ERROR @ 1227193500 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1227193500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75054552684115029173597384130678784682403827726403112677085437787236659950592 4603
UVM_ERROR @ 2574558880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2574558880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90844501933621072272276691459018344991788628733676699361366334898324590245139 12930
UVM_ERROR @ 17930230823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17930230823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16079020116911709962541477049466491320393645164089418102549484366663189631537 4226
UVM_ERROR @ 1952146540 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1952146540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49425578643860862321320548931562297696267476800596555302334842565529162697139 157
UVM_ERROR @ 3223693595 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3223693595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14490495385695698269836921134849676597443829853419907422785955903791495978440 1713
UVM_ERROR @ 4188859125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4188859125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79906047016513074487783795694546286808576474036053103250672354749477165081754 151
UVM_ERROR @ 105166778 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 105166778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 111818707147133149455163918380967260634606162341630033084723283863926651951088 3554
UVM_ERROR @ 14097397544 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14097397544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32605328299307338120480915469455222262943121342177828776158060011583982031137 1153
UVM_ERROR @ 701950315 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 701950315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80837000821477254184743200916500107820013314197341164429347299238676357660461 1551
UVM_ERROR @ 17529351670 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17529351670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20027870460844288678209592034042009800294187959541151932054478386000600755954 7319
UVM_ERROR @ 2211870864 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2211870864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44908843091759934737232117024717052631402344784975725523731143043432779789142 803
UVM_ERROR @ 2326216224 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2326216224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43565766669805392715328054250928802073833786509300171884105663642428638812642 505
UVM_ERROR @ 1717330328 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1717330328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53193130420282128342530697869629531373410819394542791496564658161034867010039 1220
UVM_ERROR @ 1503088615 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1503088615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 97042826183044106186549804230914545253585203103346601272245244786036513457666 1806
UVM_ERROR @ 8993188306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8993188306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90544762639270869737025771577448966760023563156886010155256903562650279612690 1076
UVM_ERROR @ 1985014158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1985014158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34780122480758440704695050180274746443416818256392529306974567120000793394125 4631
UVM_ERROR @ 1643670093 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1643670093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65461296059435481651801559154516200820913325791432638741463482208747964831271 154
UVM_ERROR @ 480991155 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 480991155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14862885392603232465103957988798262369389060422295758900570845562366741762889 808
UVM_ERROR @ 1654462631 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1654462631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107566640101312296975287976228616025401188613549208773888076922789471771230513 1361
UVM_ERROR @ 7206974152 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7206974152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98526904067842269616285094055640015245108837149176070019116712699082359330110 2774
UVM_ERROR @ 2635881901 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2635881901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99499443144630044078413269862721222666242320887617688980216719027028612095289 1445
UVM_ERROR @ 2882408274 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2882408274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 57765208321224339622720529208024938809940443420814828934011385334341751475254 9326
UVM_ERROR @ 16598702499 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 16598702499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---