Simulation Results: otbn

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 96.65 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.48 %
  • line
  • 99.65 %
  • branch
  • 93.37 %
  • toggle
  • 93.58 %
  • FSM
  • 100.00 %
Validation stages
V1
99.48%
V2
99.71%
V2S
98.71%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
single_binary 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 12.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 14.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 10.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 18.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 12.000s 0.000us 20 20 100.00
otbn_csr_aliasing 10.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 111.000s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 56.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 47.000s 0.000us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 68.000s 0.000us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 330.000s 0.000us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 284.000s 0.000us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 107.000s 0.000us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 24.000s 0.000us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 8.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 10.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 13.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 13.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 12.000s 0.000us 20 20 100.00
otbn_csr_aliasing 10.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 10.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 12.000s 0.000us 20 20 100.00
otbn_csr_aliasing 10.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 10.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 23.000s 0.000us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 10.000s 0.000us 5 5 100.00
otbn_controller_ispr_rdata_err 12.000s 0.000us 5 5 100.00
otbn_mac_bignum_acc_err 33.000s 0.000us 5 5 100.00
otbn_urnd_err 8.000s 0.000us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 12.000s 0.000us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 11.000s 0.000us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 62.000s 0.000us 20 20 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
passthru_mem_tl_intg_err 16 20 80.00
otbn_passthru_mem_tl_intg_err 63.000s 0.000us 16 20 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 23.000s 0.000us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 62.000s 0.000us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 107.000s 0.000us 60 60 100.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 23.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 23.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 107.000s 0.000us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 0.000us 10 10 100.00
otbn_dmem_err 23.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 9.000s 0.000us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 0.000us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 201.000s 0.000us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 201.000s 0.000us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 19.000s 0.000us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 13.000s 0.000us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 15.000s 0.000us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 15.000s 0.000us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 16.000s 0.000us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 330.000s 0.000us 9 10 90.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 12.000s 0.000us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 345.000s 0.000us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 204.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 313.000s 0.000us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 11.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 88787404256870879085216729724249823934556834476017836134335817374783319418764 111
UVM_FATAL @ 186065808 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 186065808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 44368539924805232385976351020456677925696106602497430685191239292368800010937 181
UVM_FATAL @ 175894492 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 175894492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 112501785767299866290636212034728998761071634565531517685369039685881097691306 243
UVM_FATAL @ 278056911 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 278056911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 106718384090349083340610903168888878058837631355576598389592726302182234745720 86
UVM_FATAL @ 2466004 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 2466004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 97824210736012056522531012029977960875285454067180686414149195774358308228543 86
UVM_FATAL @ 4790556 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 4790556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 113145066614651291109280766217441992720358594060275179598582822663934832302690 96
UVM_FATAL @ 52210474 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 52210474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 58283164941054719484038422106318160539011872295661895478556771291937835323154 183
UVM_FATAL @ 143676234 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 143676234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 56768579733965777811940139708625382316997460775175294959275192092749138420676 172
UVM_FATAL @ 1213687402 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1213687402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 28122381030522679568000037371258535788658199972693780668542782057451573126501 205
UVM_FATAL @ 1093818405 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1093818405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 55955495998617901844367678156136242890805374010221828753796730155735761925230 161
UVM_ERROR @ 152140909 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 152140909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 60957430555769631822450193012615292764185651496263386870718578232273052033805 245
UVM_ERROR @ 640133093 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 640133093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 38271033460366394320111989896970810620517312919375988151192941393283007739972 222
UVM_ERROR @ 411555600 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 411555600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 37012617770057709623043936402889942742275787787407226286132019847690288218198 125
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25695087 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 25695087 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 25695087 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 25695087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:138) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
otbn_rf_base_intg_err 26809144187389202850099320017033760137449647017647078571300806625294244810790 121
UVM_FATAL @ 47964882 ps: (otbn_rf_base_intg_err_vseq.sv:138) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 47964882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_stress_all_with_rand_reset 81196909667907819661441413062900210181623362058745555352976632851004095224548 165
UVM_FATAL @ 112601663 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 112601663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 33511694749742961579119659624559772912667345354498870250606173291726534473968 114
UVM_ERROR @ 9067681 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 9067681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_single 57368481837029692485199331669581408328890023287929544685085028288451812362102 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1