Simulation Results: sram_ctrl/main

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.14 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.97%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 97.670s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.020s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.230s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.020s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.450s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.020s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.020s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 353.340s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 184.650s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1548.220s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 465.700s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2587.130s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1517.450s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 121.900s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1375.080s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 111.680s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 605.170s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 101.530s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 98.390s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 116.910s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1313.170s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.240s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7245.170s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.090s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.030s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.030s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.020s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.020s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.100s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.020s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.020s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.100s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 57.130s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 3.180s 0.000us 20 20 100.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.180s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1313.170s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1313.170s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.020s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1375.080s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1375.080s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1375.080s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 121.900s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 9.920s 0.000us 44 50 88.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 57.130s 0.000us 20 20 100.00
sec_cm_mem_readback 39 50 78.00
sram_ctrl_readback_err 11.500s 0.000us 39 50 78.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 97.670s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 97.670s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1375.080s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 121.900s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 97.670s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.950s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 180.670s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 71862115711198282726735037764967942103033860808239622467410531588305903078621 100
UVM_ERROR @ 1724760 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1724760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 112645707911532811909678286606714702293722038073705815644576245077085404607744 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 5224800 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5224800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 104939871527676912055302705295892133243729870348345726452794539151498190666670 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 19189668 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 19189668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 67621754566563710430117791435729256119450058088656331673410552723640101044480 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 4678071 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 4678071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 115204741113655755009676723028727110782465440279781477682819838890605476079647 100
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 8262743ps failed at 8262743ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 8272844ps failed at 8272844ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 67034846876991257994711199839690427794108136173994496010557178661700252918412 98
UVM_ERROR @ 1345268059 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x9)
UVM_INFO @ 1345268059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 59956366604986483261837844146834052732951223821525519892699707948679567216026 98
UVM_ERROR @ 714640399 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x71)
UVM_INFO @ 714640399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44306896957607512546642278760411287062247740458854372074201918948866882167530 98
UVM_ERROR @ 2860239097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x70)
UVM_INFO @ 2860239097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12891819501241085019173598152886511991872733694867796755623657827058854232485 98
UVM_ERROR @ 2765100017 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x1c)
UVM_INFO @ 2765100017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 14511432208904755328951951059872842965170741453413620635365647466519414152392 98
UVM_ERROR @ 4107229813 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x24) != exp (0x70)
UVM_INFO @ 4107229813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 106152340334216762894415628263680266696115816483750976981942783190322795447954 98
UVM_ERROR @ 1502237708 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x79) != exp (0x5)
UVM_INFO @ 1502237708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 80909021218772615800854305815535545637143510697058146422840130193632476152090 98
UVM_ERROR @ 1945881912 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x39) != exp (0x15)
UVM_INFO @ 1945881912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 25825841978608309598964126402810397963779730215965032901180111355623935810553 98
UVM_ERROR @ 662176373 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x24) != exp (0x38)
UVM_INFO @ 662176373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 82329686613638894616592924164402825873712462826986285996798495120363606411332 98
UVM_ERROR @ 684417425 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x2)
UVM_INFO @ 684417425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 94341438370997338625111760998233588917599466197272468862053826770504363762221 98
UVM_ERROR @ 658781189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x66)
UVM_INFO @ 658781189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 19623130395687413013080953514450446793579224805665512661963890943093518924006 98
UVM_ERROR @ 717591939 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x76)
UVM_INFO @ 717591939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 104875385915991431192497082662806085816108301014167688787048783021172313414394 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1583429720 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1583429720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 96094113472977751573972333140780169535078640517454257662725985351223475121550 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2774865623 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2774865623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 64202837540553487985606649805691950772939648682542098035123934237174868685002 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1609753062 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1609753062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 57128126540989676633410690711433676865649465700568893200790041156862051530112 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 707134426 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 707134426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 54099637099188603240420869044746239020397095643758239308038648917624233180806 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1994082340 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1994082340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 25332497618147293777320629129031745876821155111913887925109013307392841987066 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2857384194 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2857384194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---