Simulation Results

Simulation Results: sram_ctrl/ret

05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.57%
V2		100.00%
V2S		94.74%
V3		96.00%

229/230 passed

99.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	101.960s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.950s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.030s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	1.810s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.030s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.310s	0.000us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.030s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	0.000us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	12.430s	0.000us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.680s	0.000us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1403.890s	0.000us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	394.520s	0.000us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	94.470s	0.000us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1300.150s	0.000us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	9.430s	0.000us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1408.230s	0.000us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	101.020s	0.000us	50	50	100.00
	sram_ctrl_partial_access_b2b	501.120s	0.000us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	102.140s	0.000us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	100.200s	0.000us	50	50	100.00
	sram_ctrl_throughput_w_readback	114.190s	0.000us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1569.780s	0.000us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.240s	0.000us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4792.650s	0.000us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.040s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.700s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.700s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.950s	0.000us	5	5	100.00
	sram_ctrl_csr_rw	1.030s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	0.000us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.090s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.950s	0.000us	5	5	100.00
	sram_ctrl_csr_rw	1.030s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	0.000us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.090s	0.000us	20	20	100.00

V2S

739/780 passed

94.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.520s	0.000us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00
	sram_ctrl_tl_intg_err	2.790s	0.000us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	2.790s	0.000us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1569.780s	0.000us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1569.780s	0.000us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.030s	0.000us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1408.230s	0.000us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1408.230s	0.000us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1408.230s	0.000us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	9.430s	0.000us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				45	50	90.00
	sram_ctrl_mubi_enc_err	1.600s	0.000us	45	50	90.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.520s	0.000us	20	20	100.00
sec_cm_mem_readback				44	50	88.00
	sram_ctrl_readback_err	1.760s	0.000us	44	50	88.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	101.960s	0.000us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	101.960s	0.000us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1408.230s	0.000us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	9.430s	0.000us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	101.960s	0.000us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.020s	0.000us	0	5	0.00

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				48	50	96.00
	sram_ctrl_stress_all_with_rand_reset	724.290s	0.000us	48	50	96.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	17524952868682169982132463006791226841949148446433243782115536646884272441202	99	UVM_ERROR @ 3235521 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3235521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	19932985965659049676957603808542864585843786891421114852568617239420964247748	102	UVM_ERROR @ 15503246 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 15503246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	53685717333557463708055406889672823697405539384164252220306618107042598197544	99	UVM_ERROR @ 3271160 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3271160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	32681307468271815029427938956932116528688006194478102459190989841547235716401	99	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 1063000 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 1063000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	sram_ctrl_sec_cm	88002657363207907125220691650677645212229916242650920789416277427937341378971	103	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 7350345ps failed at 7350345ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' UVM_ERROR @ 8074327 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 8074327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	23142584942583603574406140668016372943280982981751493966682729768338895132511	98	UVM_ERROR @ 98624704 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x55) UVM_INFO @ 98624704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	20797972802647804788489924182764472868278576185008286249685822316975521866576	98	UVM_ERROR @ 23031191 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x33) UVM_INFO @ 23031191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	60356524767306646194047331448168690428081445707063340621420119626721843513968	98	UVM_ERROR @ 35731137 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x5b) UVM_INFO @ 35731137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	49021887018141671691672088948444814631829310829746625081495435496709713828207	98	UVM_ERROR @ 48694633 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x52) UVM_INFO @ 48694633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	111058812715083980196462048327747511501960362356132819382674705248294890232797	98	UVM_ERROR @ 105178723 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x54) UVM_INFO @ 105178723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	58289767565310959784069234815554670030708314056651386199503157242640046294646	98	UVM_ERROR @ 105095786 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x2a) UVM_INFO @ 105095786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	27978014364146762934173045814217442928717249265427609358906366358876020320268	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 28527702 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 28527702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	8361306897947086833890854117551306355677855901334328603324507722488062771319	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 65281699 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 65281699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	82664858859568135382551962981866574100450125429468470457957223251147642291654	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 45437593 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 45437593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	5641158398322726450541521674154162623110981684294531295756541517116422454410	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 27021119 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 27021119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	91313584596600626234741742229105979312347516807110808639123237905479534128980	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 99330063 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 99330063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	sram_ctrl_stress_all_with_rand_reset	8237028592785437211379321247455982881834800001084049804423071558235740039224	160	UVM_ERROR @ 993636700 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 993636700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_stress_all_with_rand_reset	37895917588549567961543502972204293845036926297089745227957461895874592179002	165	UVM_ERROR @ 8160896453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 8160896453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	115784247847699139431580925012331717788047188706587060461873992924832522531991	98	UVM_ERROR @ 91797452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 UVM_INFO @ 91797452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---