Simulation Results: rstmgr_cnsty_chk

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
rstmgr_cnsty_chk_test 3.260s 10237.527us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))
rstmgr_cnsty_chk_test 90608255746954979063282644105926634385238570386287900821964424296229589676266 175
UVM_INFO @ 1800283004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1818203004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1836123004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1854043004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
rstmgr_cnsty_chk_test 49682823393050940157792200334273994424253958323764512930078212000649419353096 175
UVM_INFO @ 1752187187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1769627187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1787067187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1804507187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16