Simulation Results: sram_ctrl/ret

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.65 %
  • code
  • 95.75 %
  • assert
  • 95.88 %
  • func
  • 98.33 %
  • line
  • 99.13 %
  • branch
  • 98.10 %
  • cond
  • 92.18 %
  • toggle
  • 89.35 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.36%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 87.850s 500.784us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.030s 38.158us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.090s 16.710us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.450s 530.070us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.050s 31.335us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.250s 136.123us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.090s 16.710us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 31.335us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 14.030s 2288.717us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 7.070s 840.353us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1446.220s 51040.879us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 371.250s 8526.587us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 69.130s 18510.810us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1460.300s 20396.733us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 15.820s 2244.194us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1468.190s 110530.259us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 101.910s 712.243us 50 50 100.00
sram_ctrl_partial_access_b2b 538.190s 74463.898us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 95.800s 522.656us 50 50 100.00
sram_ctrl_throughput_w_partial_write 102.500s 580.198us 50 50 100.00
sram_ctrl_throughput_w_readback 95.780s 299.404us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1572.520s 68435.398us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.260s 37.805us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 4512.560s 60436.535us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 14.904us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.630s 298.290us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.630s 298.290us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 38.158us 5 5 100.00
sram_ctrl_csr_rw 1.090s 16.710us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 31.335us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 23.061us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 38.158us 5 5 100.00
sram_ctrl_csr_rw 1.090s 16.710us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 31.335us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 23.061us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.160s 582.198us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
sram_ctrl_tl_intg_err 3.720s 341.138us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.720s 341.138us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1572.520s 68435.398us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1572.520s 68435.398us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.090s 16.710us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1468.190s 110530.259us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1468.190s 110530.259us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1468.190s 110530.259us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 15.820s 2244.194us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 49 50 98.00
sram_ctrl_mubi_enc_err 1.480s 81.971us 49 50 98.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.160s 582.198us 20 20 100.00
sec_cm_mem_readback 50 50 100.00
sram_ctrl_readback_err 1.550s 70.772us 50 50 100.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 87.850s 500.784us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 87.850s 500.784us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1468.190s 110530.259us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 15.820s 2244.194us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 87.850s 500.784us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.150s 7.196us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
sram_ctrl_stress_all_with_rand_reset 576.670s 3473.199us 48 50 96.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 26378075561668398672547878895202045843499163367912993989739858743551325632281 105
UVM_INFO @ 7196383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 70830135380892785820498106996037239515479240107361993310612561526522378502810 100
UVM_INFO @ 20118657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 7526973049009006787897690133592317706816862926441078492103705608951481730681 99
UVM_INFO @ 15711260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 6992756123613240816670657402883484180251517769409198132223261401828016505928 99
UVM_INFO @ 20714233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 26641593239095291042661767030823142870900922659307116229488849688320936528151 99
UVM_ERROR @ 5370411 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5370411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 112535523174391899159467939588464223374235683180939090343480519729034232005770 368
UVM_INFO @ 8323398171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_stress_all_with_rand_reset 23411418434351375027508788999415851677192824070782945132778065338200198459983 223
UVM_INFO @ 5768758182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).
sram_ctrl_mubi_enc_err 62229534977457701991848480765834717793285141079529954791201887623052956585652 98
TL item was: req: (cip_tl_seq_item@3423) { a_addr: 'h1116a0e0 a_data: 'h26 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h0 a_user: 'h24b0a d_param: 'h0 d_source: 'h37 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 22721276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---