Simulation Results: sysrst_ctrl

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.12 %
  • code
  • 97.91 %
  • assert
  • 98.28 %
  • func
  • 86.17 %
  • line
  • 98.92 %
  • branch
  • 99.00 %
  • cond
  • 98.04 %
  • toggle
  • 100.00 %
  • FSM
  • 93.59 %
Validation stages
V1
100.00%
V2
97.65%
V2S
100.00%
V3
94.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sysrst_ctrl_smoke 9.130s 2110.706us 50 50 100.00
input_output_inverted 50 50 100.00
sysrst_ctrl_in_out_inverted 10.260s 2464.036us 50 50 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 6.800s 2185.937us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.670s 2313.508us 5 5 100.00
csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_hw_reset 14.860s 6017.503us 5 5 100.00
csr_rw 20 20 100.00
sysrst_ctrl_csr_rw 5.630s 2035.294us 20 20 100.00
csr_bit_bash 5 5 100.00
sysrst_ctrl_csr_bit_bash 164.300s 44133.291us 5 5 100.00
csr_aliasing 5 5 100.00
sysrst_ctrl_csr_aliasing 10.610s 2575.108us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 9.220s 2073.530us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sysrst_ctrl_csr_rw 5.630s 2035.294us 20 20 100.00
sysrst_ctrl_csr_aliasing 10.610s 2575.108us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 50 50 100.00
sysrst_ctrl_combo_detect 501.410s 157292.442us 50 50 100.00
combo_detect_with_pre_cond 96 100 96.00
sysrst_ctrl_combo_detect_with_pre_cond 657.680s 283711.542us 96 100 96.00
auto_block_key_outputs 50 50 100.00
sysrst_ctrl_auto_blk_key_output 550.150s 265033.530us 50 50 100.00
keyboard_input_triggered_interrupt 48 50 96.00
sysrst_ctrl_edge_detect 838.380s 645217.346us 48 50 96.00
pin_output_keyboard_inversion_control 50 50 100.00
sysrst_ctrl_pin_override_test 9.470s 2510.301us 50 50 100.00
pin_input_value_accessibility 50 50 100.00
sysrst_ctrl_pin_access_test 8.600s 2040.344us 50 50 100.00
ec_power_on_reset 49 50 98.00
sysrst_ctrl_ec_pwr_on_rst 465.880s 683224.134us 49 50 98.00
flash_write_protect_output 50 50 100.00
sysrst_ctrl_flash_wr_prot_out 9.930s 2608.733us 50 50 100.00
ultra_low_power_test 43 50 86.00
sysrst_ctrl_ultra_low_pwr 386.130s 2535364.090us 43 50 86.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 128.140s 42005.833us 2 2 100.00
stress_all 47 50 94.00
sysrst_ctrl_stress_all 3139.930s 1239764.364us 47 50 94.00
alert_test 50 50 100.00
sysrst_ctrl_alert_test 8.100s 2010.429us 50 50 100.00
intr_test 50 50 100.00
sysrst_ctrl_intr_test 7.560s 2012.226us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sysrst_ctrl_tl_errors 9.790s 2116.733us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sysrst_ctrl_tl_errors 9.790s 2116.733us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 14.860s 6017.503us 5 5 100.00
sysrst_ctrl_csr_rw 5.630s 2035.294us 20 20 100.00
sysrst_ctrl_csr_aliasing 10.610s 2575.108us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 46.240s 9714.247us 20 20 100.00
tl_d_partial_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 14.860s 6017.503us 5 5 100.00
sysrst_ctrl_csr_rw 5.630s 2035.294us 20 20 100.00
sysrst_ctrl_csr_aliasing 10.610s 2575.108us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 46.240s 9714.247us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
sysrst_ctrl_sec_cm 103.060s 42006.951us 5 5 100.00
sysrst_ctrl_tl_intg_err 87.950s 42425.052us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
sysrst_ctrl_tl_intg_err 87.950s 42425.052us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 47 50 94.00
sysrst_ctrl_stress_all_with_rand_reset 26.970s 8873.337us 47 50 94.00

Error Messages

   Test seed line log context
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *
sysrst_ctrl_ec_pwr_on_rst 57803708691733251253507008794647599354470209635318864727138196571838771902137 658
UVM_INFO @ 2316196396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all_with_rand_reset 26836290669466740088509549303477970611499341523050629457899518456702869997386 661
UVM_INFO @ 4507694847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 27907395506166968018761934629494993329657805634744421181327324495190101230596 659
UVM_ERROR @ 6355790810 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6355790810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 745655100657915301532255926882364317878597637006238545524182518295589570078 659
UVM_ERROR @ 4722199442 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4722199442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 60020630823325760131944752656614628850087859442146710478244780500752741358187 658
UVM_ERROR @ 3118420932 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3118420932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all 99932514560139857047525553250106270926076880177654015085664693661853038405507 674
UVM_ERROR @ 14988138292 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 14988138292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_edge_detect 91135820550296438377299176904461328914889177182324266757161088167547404988355 678
UVM_ERROR @ 4156883524 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4156883524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_edge_detect 22317145640585764523145087758330302727386986655373313725233538456766296928937 662
UVM_ERROR @ 2976865132 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2976865132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 84505133289431743178374571872847162087476591907308962942061323080789787404882 659
UVM_ERROR @ 5886044591 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5886044591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 107092432452803591831865095750875541940785897188231873933984894924542586073773 659
UVM_ERROR @ 4008227960 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4008227960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 112835339818238971841494020983908406004958868411648962032241457972339032086681 659
UVM_ERROR @ 4805281256 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4805281256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
sysrst_ctrl_stress_all 18520891370088609652447177033610311965808861937440580998227141026734823862016 668
UVM_INFO @ 7129642435 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 7654642435 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 7661044554 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
UVM_INFO @ 9659660591 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq
sysrst_ctrl_ultra_low_pwr 645812483470929644687624720996813077484953901410599266198224923125866183675 658
UVM_INFO @ 2357901249 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_ERROR @ 3663558729 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3663558729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all 29276006582643820473892392501114061245941405767387611697046472045032962392604 659
UVM_INFO @ 4498878315 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 6348878315 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 6356789414 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
UVM_INFO @ 8353894986 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*])
sysrst_ctrl_stress_all_with_rand_reset 58220604095384904448903188789072692451952415032550447107793292153659196309645 735
UVM_ERROR @ 11995818578 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 11995818578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all_with_rand_reset 84788729034601373990120467960025824217303678394843265771070911574191653677393 680
UVM_ERROR @ 6781432732 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6781432732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 108009650491977367463003629895410432761163980122535337799971779646402468491958 683
UVM_INFO @ 63724635148 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
UVM_INFO @ 63724657370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32
UVM_INFO @ 66204254796 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 66219163455 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e
sysrst_ctrl_combo_detect_with_pre_cond 59238385092217198111114114508435819141126341531286707338720060880076342209945 685
UVM_ERROR @ 45898908002 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45898908002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 59331107450212882575270962554820439746729015179819408125574804143112897893397 669
UVM_INFO @ 13413704458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13433704458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 23519981005 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x24
UVM_INFO @ 23520041611 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x14
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 8522789615778409112426388987956189958451213239205189957984238189700410790174 670
UVM_ERROR @ 15950321318 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.intr_state reset value: 0x0
UVM_INFO @ 15950321318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---