Simulation Results: clkmgr

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.43 %
  • code
  • 98.99 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.38 %
  • branch
  • 99.26 %
  • cond
  • 96.31 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.47%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.600s 262.618us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.140s 67.780us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 10.130s 2985.399us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.790s 87.341us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.950s 117.787us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
clkmgr_csr_aliasing 1.790s 87.341us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.300s 86.836us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.890s 519.755us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 2.280s 257.937us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.250s 44.752us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.600s 262.618us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 12.710s 2361.396us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 14.170s 2419.359us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 12.710s 2361.396us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 53.010s 11356.271us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.650s 204.943us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 3.350s 574.516us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 3.350s 574.516us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.140s 67.780us 5 5 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
clkmgr_csr_aliasing 1.790s 87.341us 5 5 100.00
clkmgr_same_csr_outstanding 1.680s 159.146us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.140s 67.780us 5 5 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
clkmgr_csr_aliasing 1.790s 87.341us 5 5 100.00
clkmgr_same_csr_outstanding 1.680s 159.146us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 22 25 88.00
clkmgr_sec_cm 2.640s 317.190us 2 5 40.00
clkmgr_tl_intg_err 3.130s 231.558us 20 20 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 2.130s 432.867us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 2.130s 432.867us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 2.130s 432.867us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 2.130s 432.867us 20 20 100.00
shadow_reg_update_error_with_csr_rw 17 20 85.00
clkmgr_shadow_reg_errors_with_csr_rw 4.340s 1228.137us 17 20 85.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 3.130s 231.558us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 12.710s 2361.396us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 14.170s 2419.359us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 2.130s 432.867us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.800s 126.120us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
clkmgr_lc_ctrl_intersig_mubi 1.410s 119.958us 49 50 98.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 2.390s 343.566us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 46 50 92.00
clkmgr_clk_handshake_intersig_mubi 1.890s 156.694us 46 50 92.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.870s 271.287us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
sec_cm_idle_ctr_redun 2 5 40.00
clkmgr_sec_cm 2.640s 317.190us 2 5 40.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.150s 142.070us 20 20 100.00
prim_count_check 2 5 40.00
clkmgr_sec_cm 2.640s 317.190us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 8.680s 1157.328us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 110.030s 42595.829us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 93445195067284022651770883168901676198722874105483031797576940061582716610329 74
UVM_ERROR @ 5744801 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 5744801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 42128176626421993485192505448759525130566261037243536319058882301012693384418 74
UVM_ERROR @ 39759420 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (8 [0x8] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 39759420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 6905085858748246567021334474021980060079363659462626038888525913543692733005 74
UVM_ERROR @ 43731479 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (7 [0x7] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 43731479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 34407858475077915736518435367768421547110899035678935093160310049905568834846 74
UVM_ERROR @ 19572395 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (1 [0x1] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 19572395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 89802439245532498538397331966854892155573452448868286318910499051016576360749 82
UVM_ERROR @ 7388917 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 7388917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 60088661530584109654570772246438996509566988380204673551896822052814060048967 97
UVM_ERROR @ 55810742 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 55810742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 12121070269295498176487760021143572609291422817420578099804877679972915535067 87
UVM_ERROR @ 12869839 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 12869839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(step_down || maybe_divided_clk)'
clkmgr_lc_ctrl_intersig_mubi 92909743746446627825068400089665339070031931225405713793192452870753744267766 75
Offending '(step_down || maybe_divided_clk)'
UVM_ERROR @ 10254485 ps: (clkmgr_div_sva_if.sv:63) [ASSERT FAILED] Div4Whole_A
UVM_INFO @ 10254485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 9996412368172138800306288553105923474863833397519932292349342765903319136386 75
UVM_ERROR @ 3546047 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 3546047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 20674269883077639897396199470041687572865786972810853458595222606716853513800 76
UVM_ERROR @ 69435605 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 69435605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Check_csr_read_clear_staged_val task: check storage_err status
clkmgr_shadow_reg_errors_with_csr_rw 12937399713611465946936546038355650432605493328442164632048262874118617454623 76
UVM_ERROR @ 126033692 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: 0x0 Check_csr_read_clear_staged_val task: check storage_err status
UVM_INFO @ 126033692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---