Simulation Results: edn/edn0

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.34 %
  • code
  • 95.74 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.390s 24.309us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.840s 62.670us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.400s 25.626us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.350s 1043.635us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.220s 41.315us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.960s 71.073us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.400s 25.626us 20 20 100.00
edn_csr_aliasing 1.220s 41.315us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 101.110s 18186.294us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 101.110s 18186.294us 300 300 100.00
genbits 300 300 100.00
edn_genbits 101.110s 18186.294us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.450s 19.708us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.580s 27.885us 200 200 100.00
errs 100 100 100.00
edn_err 1.480s 36.543us 100 100 100.00
disable 92 100 92.00
edn_disable 1.270s 16.139us 50 50 100.00
edn_disable_auto_req_mode 8.960s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 5.640s 360.644us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.620s 12.647us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.690s 118.499us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.680s 109.572us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.680s 109.572us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.840s 62.670us 5 5 100.00
edn_csr_rw 1.400s 25.626us 20 20 100.00
edn_csr_aliasing 1.220s 41.315us 5 5 100.00
edn_same_csr_outstanding 1.680s 37.289us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.840s 62.670us 5 5 100.00
edn_csr_rw 1.400s 25.626us 20 20 100.00
edn_csr_aliasing 1.220s 41.315us 5 5 100.00
edn_same_csr_outstanding 1.680s 37.289us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
edn_tl_intg_err 2.370s 139.708us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.370s 18.682us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.580s 27.885us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.580s 27.885us 200 200 100.00
edn_sec_cm 8.720s 1064.086us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.580s 27.885us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.370s 139.708us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 43 50 86.00
edn_stress_all_with_rand_reset 77.060s 11696.920us 43 50 86.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 71983249158158669320976659117878790466944517103977903466259516864123940630334 292
UVM_ERROR @ 1959517638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1959517638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 12965614384676706845160115854864559733796475943309085311827970265698612332825 212
UVM_ERROR @ 2314937886 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2314937886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 115103510567209341545558794323662433220438588570053575175646195880899269188479 135
UVM_ERROR @ 1110538856 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1110538856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102082299974728668312389335165892182498996854003071389229019198214879927118097 188
UVM_ERROR @ 467429403 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 467429403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 14312615239575738906798358003577150072716198851275757101647076406551179953597 125
UVM_ERROR @ 566890927 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 566890927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 1829580367345728489436579284664481344709589502877470222541048745316023838829 119
UVM_ERROR @ 112745471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 112745471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 50040590625940253627391651463208408132093021269892089550746300464243492743906 125
UVM_ERROR @ 133440763 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 133440763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 94396765128045700137592129237113357904003128317530033680115857228417013719369 88
UVM_FATAL @ 47126476 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x004886a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 47126476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69723242473364265531415990306192221604963925252831916503423733339009951147027 88
UVM_FATAL @ 27479326 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00a39652 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 27479326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19320098248719976827623906589381678415040317538634074621858357122149918451515 88
UVM_FATAL @ 32080321 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f01672 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 32080321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 20827448930033091099191691742335094144256155907870048558642293830685215728182 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 70867776010660685390852853771368817344235968453616526680155411807704750226349 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 27332694683605836618356838893844622470730677831683009544278490760443783719600 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65365878780493299918008489139657497833916960790565424887145319565685713859791 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 57729104598268568127272778598100558562601785182813570159816942238621530848534 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---