Simulation Results: edn/edn1

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 96.39 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.59%
V2S
100.00%
V3
84.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.580s 129.317us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.890s 19.219us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.860s 44.537us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.160s 500.560us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.160s 139.727us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.450s 30.522us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.860s 44.537us 20 20 100.00
edn_csr_aliasing 1.160s 139.727us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 87.370s 9153.647us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 87.370s 9153.647us 300 300 100.00
genbits 300 300 100.00
edn_genbits 87.370s 9153.647us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.410s 26.097us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.690s 124.218us 200 200 100.00
errs 100 100 100.00
edn_err 1.780s 91.247us 100 100 100.00
disable 96 100 96.00
edn_disable 1.580s 12.774us 50 50 100.00
edn_disable_auto_req_mode 2.940s 500.000us 46 50 92.00
stress_all 50 50 100.00
edn_stress_all 4.200s 281.098us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.850s 15.381us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 2.810s 253.033us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.790s 469.318us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.790s 469.318us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.890s 19.219us 5 5 100.00
edn_csr_rw 0.860s 44.537us 20 20 100.00
edn_csr_aliasing 1.160s 139.727us 5 5 100.00
edn_same_csr_outstanding 1.060s 56.754us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.890s 19.219us 5 5 100.00
edn_csr_rw 0.860s 44.537us 20 20 100.00
edn_csr_aliasing 1.160s 139.727us 5 5 100.00
edn_same_csr_outstanding 1.060s 56.754us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
edn_tl_intg_err 3.040s 1077.417us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.590s 83.569us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.690s 124.218us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.690s 124.218us 200 200 100.00
edn_sec_cm 4.060s 451.064us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.690s 124.218us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.040s 1077.417us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 42 50 84.00
edn_stress_all_with_rand_reset 102.600s 39659.664us 42 50 84.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 88645640507623265163619742583280841447414812217950371129458359226850540689008 131
UVM_ERROR @ 1050261592 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1050261592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 109158645237969434564867750010709747074870779890164837964543075412867229789 275
UVM_ERROR @ 2346611266 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2346611266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102348489423447492241348874434246739883878245962214757981639720608177258946371 247
UVM_ERROR @ 2580705990 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2580705990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 94550239914888380688371207440652522106487592236737058481046780290950691143783 170
UVM_ERROR @ 1685373375 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1685373375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 90846350350722172701332383740232974489826285972421115862782590641794652562103 183
UVM_ERROR @ 1988741287 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1988741287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 48309436332995635924021093835780903631358448743961687073022058971757251838736 255
UVM_ERROR @ 2782397303 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2782397303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 10283223631132552420441569804776250616211589973665860498905905690105028201572 310
UVM_ERROR @ 4021599882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4021599882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 59488659548173129356568230135394515752097434241428892081105225101587087277165 315
UVM_ERROR @ 2012934235 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2012934235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 49688269254058933218237883949364704430988845945824442583025779838299430285244 88
UVM_FATAL @ 56026247 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 56026247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 30862080219324254650561203876756153213528595355775232854180884519426625819246 88
UVM_FATAL @ 13522720 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001903 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 13522720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 42744164679334504667975270059918502334488853606939574623876413499141974287943 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 79440059141451660006747916004885301192793622353597465850004217832696859876712 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---