Simulation Results: keymgr

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.77 %
  • code
  • 98.45 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 97.92 %
  • toggle
  • 98.60 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.48%
V2S
99.74%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 21.170s 3435.222us 50 50 100.00
random 50 50 100.00
keymgr_random 70.000s 9983.052us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.650s 63.358us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 13.050s 858.761us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 8.050s 2055.687us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.120s 182.674us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_csr_aliasing 8.050s 2055.687us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 80.010s 8011.414us 50 50 100.00
sideload 199 200 99.50
keymgr_sideload 31.630s 1772.268us 50 50 100.00
keymgr_sideload_kmac 28.030s 1627.121us 49 50 98.00
keymgr_sideload_aes 36.180s 4106.525us 50 50 100.00
keymgr_sideload_otbn 34.900s 1410.997us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 8.830s 376.556us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 7.650s 352.410us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 5.510s 109.458us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 61.000s 3032.956us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 48.320s 10497.213us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 20.020s 2641.833us 50 50 100.00
stress_all 48 50 96.00
keymgr_stress_all 169.780s 8715.472us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.310s 15.412us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.300s 82.086us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.280s 1990.485us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.280s 1990.485us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.650s 63.358us 5 5 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_csr_aliasing 8.050s 2055.687us 5 5 100.00
keymgr_same_csr_outstanding 3.440s 100.369us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.650s 63.358us 5 5 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_csr_aliasing 8.050s 2055.687us 5 5 100.00
keymgr_same_csr_outstanding 3.440s 100.369us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 8.720s 325.906us 20 20 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.490s 398.062us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.490s 398.062us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.490s 398.062us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.490s 398.062us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.420s 812.372us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.720s 325.906us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.490s 398.062us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 80.010s 8011.414us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_random 70.000s 9983.052us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_random 70.000s 9983.052us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.820s 98.017us 20 20 100.00
keymgr_random 70.000s 9983.052us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 7.650s 352.410us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 48.320s 10497.213us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 48.320s 10497.213us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 70.000s 9983.052us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 21.750s 2450.771us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 43.810s 1392.901us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 7.650s 352.410us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.810s 1392.901us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.810s 1392.901us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.810s 1392.901us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.650s 1782.566us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 43.810s 1392.901us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
keymgr_stress_all_with_rand_reset 16.870s 2288.718us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 106582780067397292119622394614018807953709088131693202589388376543988837922612 285
UVM_ERROR @ 566448772 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 566448772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 77452874645481256213298740768053256706471296533759442188455905708206120682599 141
UVM_ERROR @ 131527513 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 131527513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61018067445561646796897096539784565351060117743990053924596047329957891426170 558
UVM_ERROR @ 298804057 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 298804057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78586350800570344406383972003052195507652337535673028939490716880437014828774 661
UVM_ERROR @ 242332232 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 242332232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 102445944209853896522961149129586726129934524477091793842009591223034879897356 127
UVM_ERROR @ 123273529 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123273529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 86876988279119397003467907683038484117772356482565771718267351448735172460196 340
UVM_ERROR @ 140327871 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 140327871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 5803711835079371027275666746963132878118065469891868205835202433352935684804 585
UVM_ERROR @ 2250836956 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2250836956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37100569204750366556774077756299184426504816268596831241797874134458389037116 112
UVM_ERROR @ 260032711 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 260032711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107063744080084049169065006954151633463836784287646885073077347477357225642545 577
UVM_ERROR @ 251382765 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 251382765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 617246039558221018789692238350553601306568258721412026499461080239535384952 101
UVM_ERROR @ 211652650 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 211652650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46466114382775703474004431301394503432597148825291488598209137804594658905316 174
UVM_ERROR @ 182774737 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 182774737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40166436035058682275094935600269791316326430844126123826454153194474320083176 372
UVM_ERROR @ 909415616 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 909415616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 693556971724629005145444560095652652773819979886480313832983417755254282982 267
UVM_ERROR @ 178795217 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 178795217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98198058380915947022518599380436952661583196137829538583631701399112968423177 1058
UVM_ERROR @ 1798561054 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1798561054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 27616917084991369506320861311906533331818151829766971035369468728151861976513 279
UVM_ERROR @ 240991985 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 240991985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 115620343973146063759941950635730872151307137862314793203025564326855584346839 616
UVM_ERROR @ 263993844 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 263993844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50364277583242311517225826054088949751655782637058382896986610912776718278706 849
UVM_ERROR @ 854457363 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 854457363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43241123615323376809494367762380244084478909417564690064685313106220411557862 292
UVM_ERROR @ 182247138 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 182247138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49840129340541277671183315712631013752086175866067117852338984445682140850851 417
UVM_ERROR @ 493797421 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 493797421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51204370856235677374481482718159545594419662745384057755343527492018442373066 438
UVM_ERROR @ 941650272 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 941650272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95671998857729006988347684966670176489818316839223653855255898118533872131907 161
UVM_ERROR @ 132907649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 132907649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98987190920692991888144427117433589954792562451905983551848416878270577523639 612
UVM_ERROR @ 729874772 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 729874772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108580225072990984243620882843312239315936366669740988606784518805564407437635 487
UVM_ERROR @ 463781432 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 463781432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64554702317872151137563910340069811181173798053309616393930797343297974812479 148
UVM_ERROR @ 318107345 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 318107345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94008686386815400197123944125047808851518020802956372485711918183471295779588 442
UVM_ERROR @ 1458428553 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1458428553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56629566033773857567253383323837314961478083539995194742634774639168011513375 432
UVM_ERROR @ 198853909 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 198853909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_lc_disable 96163788983143412291778782928590059816771414594121564659733093170633048038932 178
UVM_ERROR @ 137221062 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
UVM_INFO @ 137221062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 72812200655166136959671203404329935058156796865573961577498740408355563056940 1994
UVM_ERROR @ 730577196 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_5
UVM_INFO @ 730577196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 104532480567550708913291754333865114977119545613606467910291045645829862535916 612
UVM_ERROR @ 667848103 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 667848103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_sideload_kmac 41141627527058858177527748720738059356395412951058007505865347439167209579323 88
UVM_ERROR @ 5291596 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 5291596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---