Simulation Results: kmac/unmasked

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 92.05 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 71.90 %
Validation stages
V1
100.00%
V2
97.79%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 54.440s 16741.889us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.620s 37.794us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.420s 27.586us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 21.170s 1569.334us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.070s 957.001us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.240s 72.348us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.420s 27.586us 20 20 100.00
kmac_csr_aliasing 7.070s 957.001us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.130s 12.979us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.990s 39.566us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3730.620s 565892.132us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 995.140s 27868.899us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1753.080s 212936.716us 5 5 100.00
kmac_test_vectors_sha3_256 2002.130s 302899.612us 5 5 100.00
kmac_test_vectors_sha3_384 1453.030s 383205.595us 5 5 100.00
kmac_test_vectors_sha3_512 889.830s 291977.748us 5 5 100.00
kmac_test_vectors_shake_128 2115.040s 422289.173us 5 5 100.00
kmac_test_vectors_shake_256 1676.750s 85085.500us 5 5 100.00
kmac_test_vectors_kmac 2.960s 446.125us 5 5 100.00
kmac_test_vectors_kmac_xof 2.910s 292.860us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 411.620s 21817.831us 50 50 100.00
app 50 50 100.00
kmac_app 284.770s 93469.779us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 268.880s 73181.111us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 354.980s 146842.565us 50 50 100.00
error 50 50 100.00
kmac_error 408.860s 41346.688us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 10.850s 2826.161us 49 50 98.00
sideload_invalid 34 50 68.00
kmac_sideload_invalid 136.440s 10016.764us 34 50 68.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.710s 27815.153us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 45.040s 10558.177us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 73.190s 21320.025us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 33.090s 3135.645us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2645.100s 1062368.227us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.180s 16.650us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.290s 233.708us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.630s 573.896us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.630s 573.896us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.620s 37.794us 5 5 100.00
kmac_csr_rw 1.420s 27.586us 20 20 100.00
kmac_csr_aliasing 7.070s 957.001us 5 5 100.00
kmac_same_csr_outstanding 3.160s 330.380us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.620s 37.794us 5 5 100.00
kmac_csr_rw 1.420s 27.586us 20 20 100.00
kmac_csr_aliasing 7.070s 957.001us 5 5 100.00
kmac_same_csr_outstanding 3.160s 330.380us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.760s 93.129us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.760s 93.129us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.760s 93.129us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.760s 93.129us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.810s 1761.123us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.910s 748.980us 20 20 100.00
kmac_sec_cm 64.460s 6176.224us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.910s 748.980us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 33.090s 3135.645us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 54.440s 16741.889us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 411.620s 21817.831us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.760s 93.129us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 64.460s 6176.224us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 64.460s 6176.224us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 64.460s 6176.224us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 54.440s 16741.889us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 33.090s 3135.645us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 64.460s 6176.224us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 265.180s 49914.250us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 54.440s 16741.889us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 174.250s 31638.222us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 83131800482880325005239701962667688870736963685448624412697377077034729605799 84
UVM_FATAL @ 10197032846 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfa00f000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10197032846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 114242891659394914363711765076384197710293432549080890439892804528851195422145 84
UVM_FATAL @ 10150837775 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x812c4000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10150837775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 54289289035411607764508053405082300480174598368635775720379796429239409804771 85
UVM_FATAL @ 10157990884 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x222be000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10157990884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 35936300754597150484173946614344149908517726555075391862849588489548712839280 78
UVM_FATAL @ 10036030091 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x12a82000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10036030091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 98505291407665226409006400316811236225038755679803189254189012342086049297801 78
UVM_FATAL @ 10091636076 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe1cd2000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10091636076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 7459382606223909810874654209232492520269837165392676034648792899139451985966 78
UVM_FATAL @ 10177239276 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xab7c9000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10177239276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 41719073535143103353405314970575991693212605107777871739108082641507336138573 370
UVM_ERROR @ 15403276987 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 15403276987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 475327267102910534693644635893283968049929436920512214606095209854161304183 85
UVM_FATAL @ 10058214095 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x86223000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10058214095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 2929877357131983109680118379444551108038120666025344344711045491195156242103 84
UVM_FATAL @ 10062253370 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6f4c4000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10062253370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 63142212019742284352817742633021127334244315053251874277077137438151404856110 100
UVM_ERROR @ 1911736187 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1911736187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 73479464775702915266478763579440377904678921300088649188168646314029608349681 89
UVM_FATAL @ 10200646323 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x84343000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10200646323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 101355055823610565233112570556458262259542432342907478370765625110795471997403 87
UVM_FATAL @ 10227523143 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa69b0000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10227523143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 90757797874649853828939119881365709331048090018043724749313714950470472656846 79
UVM_FATAL @ 10022824138 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb75fd000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10022824138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 20244828509000482745023537167645494996034538537529751179237749424538449439115 79
UVM_FATAL @ 10041963463 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x74560000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10041963463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 69816412396280973130566231447309465391162244931867539208743334848866201809631 79
UVM_FATAL @ 10016763668 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x97cde000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10016763668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 85517140773746559156175687276532461085783395450460613261291807221925989371636 79
UVM_FATAL @ 10167094301 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb74ef000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10167094301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 113602475010711449697854248766740276275947932843719042853025769621539535865934 89
UVM_ERROR @ 513065320 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 513065320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 88614227866808132050194567380539423732592634065135617018818158030759516019482 90
UVM_FATAL @ 10436173892 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9b8a9000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10436173892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 78787119840654653557781601059861870187787056629475311292471624188695055516782 81
UVM_FATAL @ 10094165101 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd9235000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10094165101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---