Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 86.36 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.12 %
  • cond
  • 81.71 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.040s 133.224us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.300s 68.273us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.360s 54.419us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.270s 181.779us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.800s 145.203us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.100s 23.832us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.360s 54.419us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 145.203us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.840s 182.603us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 19.920s 1745.260us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.330s 19.982us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.650s 151.057us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_errors 48 50 96.00
lc_ctrl_errors 16.650s 587.428us 48 50 96.00
security_escalation 256 260 98.46
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_prog_failure 4.650s 151.057us 50 50 100.00
lc_ctrl_errors 16.650s 587.428us 48 50 96.00
lc_ctrl_security_escalation 13.800s 2478.126us 50 50 100.00
lc_ctrl_jtag_state_failure 58.180s 15952.470us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.400s 3080.279us 20 20 100.00
lc_ctrl_jtag_errors 59.200s 5752.467us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_csr_hw_reset 3.940s 187.472us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.490s 559.752us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.410s 1729.749us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.640s 705.730us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.800s 31.448us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.280s 1009.184us 10 10 100.00
lc_ctrl_jtag_alert_test 2.350s 122.773us 10 10 100.00
lc_ctrl_jtag_smoke 13.240s 680.547us 20 20 100.00
lc_ctrl_jtag_state_post_trans 32.910s 6630.756us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.400s 3080.279us 20 20 100.00
lc_ctrl_jtag_errors 59.200s 5752.467us 18 20 90.00
lc_ctrl_jtag_access 18.230s 885.864us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 39.900s 1162.132us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 13.390s 1343.998us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.650s 21.699us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 547.070s 90601.682us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.700s 74.796us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.290s 153.432us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.290s 153.432us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.300s 68.273us 5 5 100.00
lc_ctrl_csr_rw 1.360s 54.419us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 145.203us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.180s 40.795us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.300s 68.273us 5 5 100.00
lc_ctrl_csr_rw 1.360s 54.419us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 145.203us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.180s 40.795us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 4.160s 851.718us 20 20 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.160s 851.718us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 19.920s 1745.260us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.470s 584.662us 50 50 100.00
lc_ctrl_sec_cm 9.590s 907.884us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 13.800s 2478.126us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.840s 182.603us 50 50 100.00
lc_ctrl_jtag_state_post_trans 32.910s 6630.756us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 23.230s 957.495us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 23.230s 957.495us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 21.360s 821.063us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.610s 648.837us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.610s 648.837us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 117.860s 5910.568us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 6200108580904684745114867585872894466100017435644176271611490461098697711653 1022
UVM_ERROR @ 8309429581 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8309429581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53177750122054620162457485919984127827650734542087448342977799710217797798977 323
UVM_ERROR @ 212963616 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 212963616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76130748102817926217637248715620576502062501352396122821429817900349190596826 206
UVM_ERROR @ 4244835143 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4244835143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23404328405555761963159681047530465820661974946694243474037991654909436040557 6186
UVM_ERROR @ 5661921665 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5661921665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98096569765004782086989774472385956830598034819023541129714609871292543306832 507
UVM_ERROR @ 985549008 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 985549008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56020882120093629083111385070451420397739160290655954441419965976781579562336 10169
UVM_ERROR @ 20487648175 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20487648175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42497912843130628478853902693439203545400562325146801636965630440824603424826 4302
UVM_ERROR @ 5218781707 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5218781707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2352081200949655847504076901033924811340288191933238609018767521467454142445 6326
UVM_ERROR @ 16979375252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16979375252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37877728900342927146615770617613180944237299804611672824470842409939495203071 963
UVM_ERROR @ 1008336630 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1008336630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63485896244186653914445472659182760003695088313794832963999129949300493374642 1357
UVM_ERROR @ 7867899405 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7867899405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54458473257406982287350239506935631795684615570989133127037214868467838494676 2432
UVM_ERROR @ 1160943450 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1160943450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55222355542485103544277106185998574001817720323419589655598580221959927111028 2966
UVM_ERROR @ 4995618390 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4995618390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48052689811669146833741940311937917021792550626570659183454337677174045138454 5933
UVM_ERROR @ 3575225652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3575225652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63927005243630966430060469658366501780390453684712541316442023801425615808762 151
UVM_ERROR @ 551425941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 551425941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28765567144795019832163692224950093504419402940351796688913919424380905334061 259
UVM_ERROR @ 1971460471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1971460471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65052284598164375239310651577092980080074694143298671798400059102895590724036 986
UVM_ERROR @ 1792237441 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1792237441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90153037172540602503886491970342544092270709992738575698513125526315568165022 3555
UVM_ERROR @ 3912223775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3912223775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49009797794285910434877163209513593552955004590884416114978209520936944822478 610
UVM_ERROR @ 6436821315 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6436821315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14433555862822437589312307447426964227937855778403448125984834659638743478554 749
UVM_ERROR @ 2140253877 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2140253877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105577720578697153025072550446608568209084126269680291038176520736182512117033 158
UVM_ERROR @ 1102091733 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1102091733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 30751398436535226523578039621945951141322612180330052781315799859208167475158 2859
UVM_ERROR @ 1249520764 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1249520764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 15557223999599899799564764193560868852822599743331691871280541107466949566793 2278
UVM_ERROR @ 867324093 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 867324093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16839319839700671592609919282966043713513413852922443785483563457108676069408 12015
UVM_ERROR @ 1440762997 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1440762997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 60888817102700469454361504798788832064900759281141502851517675160664537385876 3979
UVM_ERROR @ 7986489871 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7986489871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 36851352367241722453162746135677198208283712541740615814162741721553682310689 2510
UVM_ERROR @ 3173655833 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3173655833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 14463188182754930660499196114677204355217837065284360777621013186004329656730 2634
UVM_ERROR @ 324478306 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 324478306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 41837138943217599271863274929022595567498884420567485251641112570100671464367 2250
UVM_ERROR @ 317816140 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 317816140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 59773256918206061393032913066451771471392410134908559164235680809647308719194 13635
UVM_ERROR @ 90601682461 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 90601682461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*
lc_ctrl_stress_all_with_rand_reset 38263061800995440358144701296104123928583260293242352606914087422641797959109 4510
UVM_ERROR @ 2746275214 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestLocked5
UVM_INFO @ 2746275214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 110973244649905957559268598471998357345641927472451275689381657708323276432466 2955
UVM_ERROR @ 3742682431 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 3742682431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
lc_ctrl_stress_all_with_rand_reset 58294169100185659181061709374902876878067601245529166237988484282838958271776 None
Job timed out after 180 minutes
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
lc_ctrl_stress_all_with_rand_reset 98351263115841867987535495522732662703118502967007598815147896221428265254038 1242
UVM_FATAL @ 584394557 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_state_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 584394557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107391900490629888159873844658792582252363009057568865244492705874008856399091 9785
UVM_FATAL @ 11489854660 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_prog_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 11489854660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---