Simulation Results: rstmgr_cnsty_chk

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
rstmgr_cnsty_chk_test 2.990s 9812.208us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))
rstmgr_cnsty_chk_test 99764600549097455322590770279227229705812562470475447910442293449804650881871 175
UVM_ERROR @ 1750616094 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 1768216094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1785816094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1803416094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1821016094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
rstmgr_cnsty_chk_test 16660068807378681460929661910517301372146387625919196997466432351920750625388 175
UVM_ERROR @ 2020408927 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 2040728927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2061048927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2081368927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2101688927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16