Simulation Results: spi_host

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 57.000s 1649.674us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 41.980us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 18.617us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 3.000s 157.559us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 93.383us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 55.817us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 18.617us 20 20 100.00
spi_host_csr_aliasing 2.000s 93.383us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 25.037us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 71.701us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 47.682us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 42.000s 2617.617us 50 50 100.00
spi_host_error_cmd 2.000s 21.862us 50 50 100.00
spi_host_event 796.000s 49631.979us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 7.000s 1393.268us 50 50 100.00
speed 50 50 100.00
spi_host_speed 7.000s 1393.268us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 7.000s 1393.268us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 101.000s 2669.910us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 19.769us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 7.000s 1393.268us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 7.000s 1393.268us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 57.000s 1649.674us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 57.000s 1649.674us 50 50 100.00
stress_all 49 50 98.00
spi_host_stress_all 86.000s 24973.667us 49 50 98.00
spien 50 50 100.00
spi_host_spien 85.000s 8026.543us 50 50 100.00
stall 47 50 94.00
spi_host_status_stall 2205.000s 1000000.000us 47 50 94.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 46.000s 8965.570us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 42.000s 2617.617us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 16.096us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 21.959us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 112.594us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 112.594us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 41.980us 5 5 100.00
spi_host_csr_rw 2.000s 18.617us 20 20 100.00
spi_host_csr_aliasing 2.000s 93.383us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 50.529us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 41.980us 5 5 100.00
spi_host_csr_rw 2.000s 18.617us 20 20 100.00
spi_host_csr_aliasing 2.000s 93.383us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 50.529us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 168.131us 5 5 100.00
spi_host_tl_intg_err 2.000s 95.284us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 95.284us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 458.000s 34651.964us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 29491535616854224015674815903761379747659827528074967640450259710972545005567 115
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 42104803319476473898782792330764763869139804040597006360037396680844999320111 843
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: *
spi_host_status_stall 79777141614192395220991508809599146361876864653953913668362141492314952133365 1480
UVM_ERROR @ 214390782 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 214390782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_stress_all 81129352884472967666214185268756241720258849043106439578307135675311716271060 179
UVM_FATAL @ 10034632341 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x2d987ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=21
UVM_INFO @ 10034632341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
spi_host_status_stall 13239178283244714291860530010838134619355682355682494964279697261352303176806 1944
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 8492494307 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 8492494307 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=8492494000 ps
UVM_INFO @ 8492494307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---