Simulation Results: alert_handler

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.01 %
  • code
  • 98.91 %
  • assert
  • 98.88 %
  • func
  • 99.23 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.50 %
  • toggle
  • 97.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.49%
V2S
98.87%
V3
54.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 9.900s 121.066us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 9.960s 446.528us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 303.040s 22802.019us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 276.550s 8113.844us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 16.230s 228.314us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 9.960s 446.528us 20 20 100.00
alert_handler_csr_aliasing 276.550s 8113.844us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 280.220s 5705.894us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 63.100s 1111.849us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 2224.900s 47754.660us 50 50 100.00
sig_int_fail 48 50 96.00
alert_handler_sig_int_fail 62.420s 8646.060us 48 50 96.00
clk_skew 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 74.420s 1322.460us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 67.720s 2403.743us 50 50 100.00
ping_timeout 22 50 44.00
alert_handler_ping_timeout 591.200s 64449.447us 22 50 44.00
lpg 99 100 99.00
alert_handler_lpg 2558.960s 62405.590us 49 50 98.00
alert_handler_lpg_stub_clk 2249.010s 204388.714us 50 50 100.00
stress_all 49 50 98.00
alert_handler_stress_all 2484.110s 107371.992us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 35.050s 7751.345us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 4.790s 211.156us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.300s 18.257us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 22.520s 1110.534us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 22.520s 1110.534us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 9.900s 121.066us 5 5 100.00
alert_handler_csr_rw 9.960s 446.528us 20 20 100.00
alert_handler_csr_aliasing 276.550s 8113.844us 5 5 100.00
alert_handler_same_csr_outstanding 51.820s 6657.835us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 9.900s 121.066us 5 5 100.00
alert_handler_csr_rw 9.960s 446.528us 20 20 100.00
alert_handler_csr_aliasing 276.550s 8113.844us 5 5 100.00
alert_handler_same_csr_outstanding 51.820s 6657.835us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 309.220s 20680.119us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 309.220s 20680.119us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 309.220s 20680.119us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 309.220s 20680.119us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 985.930s 332908.150us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
alert_handler_tl_intg_err 72.590s 2233.195us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 72.590s 2233.195us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 309.220s 20680.119us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 64.130s 2247.497us 50 50 100.00
sec_cm_alert_intersig_diff 48 50 96.00
alert_handler_sig_int_fail 62.420s 8646.060us 48 50 96.00
sec_cm_lpg_intersig_mubi 49 50 98.00
alert_handler_lpg 2558.960s 62405.590us 49 50 98.00
sec_cm_esc_intersig_diff 48 50 96.00
alert_handler_sig_int_fail 62.420s 8646.060us 48 50 96.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2224.900s 47754.660us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2224.900s 47754.660us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 27.030s 545.581us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 50 54.00
alert_handler_stress_all_with_rand_reset 392.620s 36199.336us 27 50 54.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*])
alert_handler_sig_int_fail 47435401218606401227902990141139699979624743169403379900179945763321628228369 82
UVM_ERROR @ 175808162 ps: (alert_handler_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (99 [0x63] vs 158 [0x9e])
UVM_INFO @ 175808162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_sig_int_fail 91712310398932216565314739967284471428399559306670665711244937935335306994394 82
UVM_ERROR @ 137350863 ps: (alert_handler_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (174 [0xae] vs 65 [0x41])
UVM_INFO @ 137350863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 40887181130313060504910230475965543243592553399415761142342190658647129815723 87
UVM_ERROR @ 5723557142 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 5723557142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 52006770853875071723853859299906738233007355857677058047400124897648190894903 90
UVM_ERROR @ 11737834680 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 11737834680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 4530008042399663229125802890118959016896761878259682875154821889582106731179 123
UVM_ERROR @ 26190981559 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 26190981559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 439976404843410331802631522242816214201413294462041024352746116397602158849 87
UVM_ERROR @ 4646486358 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 4646486358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 73000952141807331113688946870222282177080143652250139950037934954623210453033 90
UVM_ERROR @ 1519939320 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 1519939320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 67859586198675821445361922451009292259162854824849471008668427004175893019445 107
UVM_ERROR @ 3927126778 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 3927126778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 28998336729368281538482766299491215802148491154913710292845555583786637929837 96
UVM_ERROR @ 10676310881 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 10676310881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 109103805868858046771746776627637728883618927833199555656466327175636696106038 84
UVM_ERROR @ 4517897179 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4517897179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 90527822862009775721319556839000297340198046024136633481988726457581459007719 112
UVM_ERROR @ 10138196575 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 10138196575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 97933693325258873734800536862990610400430433058124414787498158247841562783450 120
UVM_ERROR @ 40921017795 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 40921017795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 6603401581992969170216640209256610902014239612829013940261215730134899660413 135
UVM_ERROR @ 27450802842 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 27450802842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 114360727348144463952741387395273295238798657462392477596507229106635174141847 105
UVM_ERROR @ 15745013405 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 15745013405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 49268865959397469348597851302507211139088718756618494075325197754058137500604 87
UVM_ERROR @ 2026304648 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2026304648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 43431576669191822510139833908128899904163958332019953093234930410254573413346 87
UVM_ERROR @ 2215582068 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2215582068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 17250964798951576690688712517084069332696572096180068865886572046573386891844 147
UVM_ERROR @ 9563317058 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 9563317058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 12576387755656922708151098342666681246655000728894217263693752585465695249047 84
UVM_ERROR @ 805663246 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 805663246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 96084978387416688370654777610563493726344963683064990317889473257504868458430 105
UVM_ERROR @ 24060691939 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 24060691939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 25750635257075575046791541214902101381469558392824207162001438765744930207389 99
UVM_ERROR @ 3125282224 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 3125282224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 16563007438984514640222993466987466645820633184574224180706337563101679070051 93
UVM_ERROR @ 12418031454 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 12418031454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 86300476754979170654562180081048991149847047661687166333275788620632714815097 90
UVM_ERROR @ 12167341271 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 12167341271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 115044836038823276121728909501466096108994321337430806352748994398953321983968 93
UVM_ERROR @ 1795221848 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 1795221848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 23487006276847965345927323284557633343830695116985060996295352556715958511408 102
UVM_ERROR @ 14641914524 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 14641914524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 80307120095319266354201189676684876060742416341396620834617515105520276034059 112
UVM_ERROR @ 4625852866 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4625852866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 63752873337021759165790149342252648389843194354525959962223588894808700883652 122
UVM_ERROR @ 39964091745 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 39964091745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 95611877144723965195567840652767014611103929697551118399513211753015140506092 99
UVM_ERROR @ 30441093981 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 30441093981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 32631247271898306557464500640442510809876620639472699351880043068964260051154 129
UVM_ERROR @ 30569963428 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 30569963428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 111836186630840309520412811069268745216426015753049965538352488876087125877758 85
UVM_ERROR @ 320022486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 320022486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 113030251581108252437425203461514833245914725604148181214521255717289499792787 159
UVM_ERROR @ 3216521471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3216521471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 80409732187110206832124951745992926895451708541043845380248755581602120647138 160
UVM_ERROR @ 3395009708 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3395009708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 10302774084540959538540243557411064588056103176996704972263154892361403543625 91
UVM_ERROR @ 3668467370 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3668467370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 106210886070450513712502135066456622273554471615928746178037896036718023718124 122
UVM_ERROR @ 5594187780 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5594187780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 70692258404630496251066293907364729850934923898697481599898173119656658346262 205
UVM_ERROR @ 13744159516 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13744159516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 74037639874555426991130752561850353141213269731651159041775058576490034862891 84
UVM_ERROR @ 107821347 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107821347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 87331151787761946150462353255867893384772632340615769576980493073134415564520 120
UVM_ERROR @ 2959105121 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2959105121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22017653884113561754869273627020985367329327187897842279455000517104653858864 105
UVM_ERROR @ 10968486229 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10968486229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 108645869230773863348172715238693543191414152569906249148381631860909365308991 110
UVM_ERROR @ 820885375 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 820885375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 31509286682678612038293428613433420885749091677963909186229401148557209774056 86
UVM_ERROR @ 2309631915 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2309631915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 87294826565544917632928325012065786574994679622713555338582247636105288396312 120
UVM_ERROR @ 2158484293 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2158484293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 67236953173746428695089572319641686610504577354992661876069183569268964951827 84
UVM_ERROR @ 410562454 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 410562454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 18512860590379232822820617353441272584708647028146878158137232024549392128277 130
UVM_ERROR @ 1713957490 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1713957490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 29061275235443823998614183880473660662951944978701588427759142868696709304300 117
UVM_ERROR @ 5140884331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5140884331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 41245302273733864660872258686353983768958913995594239440895308374388793164209 188
UVM_ERROR @ 13080233284 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13080233284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 34786766521460257738943486411787680046651798659443796697019978423898948922967 105
UVM_ERROR @ 2705368778 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2705368778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 20694665480851346246637316332777137237429825320349263593493160138543965083856 140
UVM_ERROR @ 8068483932 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8068483932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 108582974364405762989034032069408738340070054516130226782915434041579576109366 90
UVM_ERROR @ 2278081631 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2278081631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 67827376708313309753856335167956292115318856423402400396719681642624471853174 96
UVM_ERROR @ 1218760149 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1218760149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 36635465559275026166496290270161877131425084494808524780973726420579670892039 212
UVM_ERROR @ 8804448900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8804448900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 80904378840760118179549565973015268821594967370275803193056311865759638423243 83
UVM_ERROR @ 220862195 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 220862195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 80911590587531065025091690335296988790798581698807123488051685360712867446305 83
UVM_ERROR @ 939584946 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 939584946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.
alert_handler_ping_timeout 102581171540500760819994124311945209513237399567835396716580965495637150477017 80
UVM_ERROR @ 134475876 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 134475876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 21781075297342620619218666132947476251673009628114439751308363081383476396290 80
UVM_ERROR @ 991243970 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 991243970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 2249052174350352378654595317946390628715504522131477506687047576371515874380 80
UVM_ERROR @ 42326721657 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 42326721657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertIntFail)
alert_handler_stress_all 34058020706102820506467089381588205288335891122396904090698955982919828477956 83
UVM_ERROR @ 2013669984 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[1]: saw 0, but expected 1. (is_int_err = 0, local_alert_type = LocalAlertIntFail)
UVM_INFO @ 2013669984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---