Simulation Results: clkmgr

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.24 %
  • code
  • 98.99 %
  • assert
  • 95.90 %
  • func
  • 87.82 %
  • line
  • 99.38 %
  • branch
  • 99.26 %
  • cond
  • 96.31 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.39%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.640s 185.147us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.360s 66.484us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 16.390s 6979.055us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 2.100s 266.632us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.920s 39.302us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
clkmgr_csr_aliasing 2.100s 266.632us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.170s 28.163us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 2.140s 343.083us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.950s 239.884us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.450s 130.201us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.640s 185.147us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 14.290s 2355.510us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 12.930s 2422.177us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 14.290s 2355.510us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 65.580s 13126.645us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.470s 67.902us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 4.480s 1013.552us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 4.480s 1013.552us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.360s 66.484us 5 5 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
clkmgr_csr_aliasing 2.100s 266.632us 5 5 100.00
clkmgr_same_csr_outstanding 1.770s 275.666us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.360s 66.484us 5 5 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
clkmgr_csr_aliasing 2.100s 266.632us 5 5 100.00
clkmgr_same_csr_outstanding 1.770s 275.666us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 22 25 88.00
clkmgr_sec_cm 3.940s 1202.419us 2 5 40.00
clkmgr_tl_intg_err 3.790s 1027.686us 20 20 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 2.560s 204.918us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 2.560s 204.918us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 2.560s 204.918us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 2.560s 204.918us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
clkmgr_shadow_reg_errors_with_csr_rw 6.490s 2334.335us 19 20 95.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 3.790s 1027.686us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 14.290s 2355.510us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 12.930s 2422.177us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 2.560s 204.918us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.650s 489.381us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.330s 239.087us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.270s 63.957us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 47 50 94.00
clkmgr_clk_handshake_intersig_mubi 1.910s 327.069us 47 50 94.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.480s 140.002us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
sec_cm_idle_ctr_redun 2 5 40.00
clkmgr_sec_cm 3.940s 1202.419us 2 5 40.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.140s 17.975us 20 20 100.00
prim_count_check 2 5 40.00
clkmgr_sec_cm 3.940s 1202.419us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 6.230s 2333.804us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 158.770s 51993.308us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 92791053688555321856131430134581436928640960446987116161225301259467059999681 147
UVM_ERROR @ 259770211 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 259770211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 5632372223424707955286522111855967394518823517362447292769025668964371343584 100
UVM_ERROR @ 76011703 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 76011703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 46776485868404342963051307738257688775228793681996963875466620512497708912669 100
UVM_ERROR @ 90865242 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 90865242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 68934913191648991576913240925458794098354440391776741842853969773296113352776 74
UVM_ERROR @ 6665145 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (11 [0xb] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 6665145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 32791115123200503586088550196986835733534838506084099338897878628918782763231 74
UVM_ERROR @ 23644519 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 23644519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 82658814288977111213748007111764311794814345597206473960149345448417407780371 74
UVM_ERROR @ 3514829 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 3514829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 36261272135400254112692992441074353989176369089000948304512544035431422678823 76
UVM_ERROR @ 609490493 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 609490493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---