Simulation Results: edn/edn0

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 95.63 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.160s 68.130us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.860s 17.021us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.870s 89.647us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.270s 256.955us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.250s 41.095us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.220s 148.542us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.870s 89.647us 20 20 100.00
edn_csr_aliasing 1.250s 41.095us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 83.400s 8704.350us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 83.400s 8704.350us 300 300 100.00
genbits 300 300 100.00
edn_genbits 83.400s 8704.350us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.190s 23.795us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.350s 31.234us 200 200 100.00
errs 100 100 100.00
edn_err 1.550s 36.229us 100 100 100.00
disable 93 100 93.00
edn_disable 1.100s 25.979us 50 50 100.00
edn_disable_auto_req_mode 14.740s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 6.550s 434.269us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.870s 16.651us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.690s 75.414us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.960s 135.017us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.960s 135.017us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.860s 17.021us 5 5 100.00
edn_csr_rw 0.870s 89.647us 20 20 100.00
edn_csr_aliasing 1.250s 41.095us 5 5 100.00
edn_same_csr_outstanding 1.190s 39.534us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.860s 17.021us 5 5 100.00
edn_csr_rw 0.870s 89.647us 20 20 100.00
edn_csr_aliasing 1.250s 41.095us 5 5 100.00
edn_same_csr_outstanding 1.190s 39.534us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
edn_tl_intg_err 3.360s 241.263us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.010s 30.632us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.350s 31.234us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.350s 31.234us 200 200 100.00
edn_sec_cm 7.770s 690.881us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.350s 31.234us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.360s 241.263us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 87.600s 8862.837us 44 50 88.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 6281933069726215544765981759270576449337711681950616453297302350411266690022 252
UVM_ERROR @ 2766291523 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2766291523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 84467808302970362656254100921757644846734805823742180267202899215629207218618 189
UVM_ERROR @ 1527166687 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1527166687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 32784188580454258583221273273907776133278786272535645155594214052660555843781 209
UVM_ERROR @ 2439649640 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2439649640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 31742178507778874036032274283933208579635085736313859778333022984864369329177 140
UVM_ERROR @ 534647079 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 534647079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98440491078343691659793071041194998030807090564946209117097135975783526750453 153
UVM_ERROR @ 1038575704 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1038575704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 3942886149535210986322600489680598851275987486218721447749939439297356380009 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9012811786234204181478928689766935322829711353575034613562470035349724126641 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106349617914791069048815483408045783745253561679334994039685667899621861498837 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43664361312998300613884176219915932699982893021310486242076708640136545435800 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 37835678309244681411108488966814491974113917747587379411185671129037459510732 88
UVM_FATAL @ 46557327 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000652 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 46557327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 68333927456815730170858129372887218084568834099867362558363891258731065295374 88
UVM_FATAL @ 68114566 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0005e952 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 68114566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 14064537228574708772012261722663475019007470776441417203576233289310358944066 88
UVM_FATAL @ 10808552 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0064e902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 10808552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (edn_scoreboard.sv:318) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts
edn_stress_all_with_rand_reset 641606137474112810709873725678330348507626021489589024710131241303178215243 204
UVM_ERROR @ 2720030356 ps: (edn_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (7 [0x7] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 2720030356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---