Simulation Results: edn/edn1

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 96.16 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
84.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.010s 26.304us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.730s 29.480us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.830s 16.833us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.970s 891.516us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.130s 40.053us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.370s 180.925us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.830s 16.833us 20 20 100.00
edn_csr_aliasing 1.130s 40.053us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 46.630s 2224.982us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 46.630s 2224.982us 300 300 100.00
genbits 300 300 100.00
edn_genbits 46.630s 2224.982us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.210s 31.307us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.260s 162.807us 200 200 100.00
errs 100 100 100.00
edn_err 1.210s 49.197us 100 100 100.00
disable 93 100 93.00
edn_disable 1.010s 17.830us 50 50 100.00
edn_disable_auto_req_mode 4.090s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 4.630s 346.440us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.840s 14.509us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.590s 241.761us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.070s 1972.229us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.070s 1972.229us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.730s 29.480us 5 5 100.00
edn_csr_rw 0.830s 16.833us 20 20 100.00
edn_csr_aliasing 1.130s 40.053us 5 5 100.00
edn_same_csr_outstanding 1.080s 78.453us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.730s 29.480us 5 5 100.00
edn_csr_rw 0.830s 16.833us 20 20 100.00
edn_csr_aliasing 1.130s 40.053us 5 5 100.00
edn_same_csr_outstanding 1.080s 78.453us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
edn_tl_intg_err 1.820s 259.588us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.870s 49.906us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.260s 162.807us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.260s 162.807us 200 200 100.00
edn_sec_cm 3.760s 417.048us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.260s 162.807us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 1.820s 259.588us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 42 50 84.00
edn_stress_all_with_rand_reset 86.080s 6795.103us 42 50 84.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 65594406300265161512015377176380234864850802392434788953363405164583516774029 176
UVM_ERROR @ 950368198 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 950368198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 68150366183526541032161029071393045984261282093565406309930144047285671840376 194
UVM_ERROR @ 1763196578 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1763196578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 4243945570864609902730612239926246774034882294078479896771945099460183430352 178
UVM_ERROR @ 1413437576 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1413437576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 59072461334350053088028349218824107186837465667806586263645336813328233228327 242
UVM_ERROR @ 2476201769 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2476201769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46902621640183976992413346142668654274876360107014935917776596176348833918135 117
UVM_ERROR @ 365335937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 365335937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46277426972569271995810524900002514899632572932792753076432305449529543644834 216
UVM_ERROR @ 1341673799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1341673799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 34840436809507305716587253909605186666824012265176736481998819200574841201507 131
UVM_ERROR @ 1328691252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1328691252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 13533169447460524614963215583469895712364832386096832442329672620886308722767 166
UVM_ERROR @ 918946567 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 918946567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 14566726269345335219917790387800596654171493332627980793278064081862353491828 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 77709406921185683778165206897189083071217323720895280918312665348948760401030 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2156371964551935425939398186442415273267242138951256185145797927368861678093 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 13654275453334667145365825275380389230768446946981238779290219536403627695204 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 736273794713543758852168988071767425145956787040880847663880278383375352614 88
UVM_FATAL @ 20169676 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00340612 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 20169676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72377768634257816501414941058074653260913830863682312688665474549210531433194 88
UVM_FATAL @ 21881790 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0091e972 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 21881790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 97583751866100770226717773696867745043120837858820556691039454894271381885482 88
UVM_FATAL @ 42901804 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00e64662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 42901804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---