Simulation Results: keymgr

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 98.96 %
  • assert
  • 97.72 %
  • func
  • 91.23 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.12 %
  • toggle
  • 98.48 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
64.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 18.420s 14768.281us 50 50 100.00
random 50 50 100.00
keymgr_random 46.680s 2363.793us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.940s 32.258us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 25.670s 25539.889us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 15.390s 521.899us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.580s 45.472us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_csr_aliasing 15.390s 521.899us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 70.750s 1993.645us 50 50 100.00
sideload 199 200 99.50
keymgr_sideload 14.880s 1038.493us 50 50 100.00
keymgr_sideload_kmac 31.550s 1474.582us 50 50 100.00
keymgr_sideload_aes 47.330s 12323.871us 50 50 100.00
keymgr_sideload_otbn 50.610s 8100.084us 49 50 98.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 10.290s 483.239us 50 50 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 5.860s 670.734us 50 50 100.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 9.240s 4366.016us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 58.500s 4780.067us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 32.340s 8910.446us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 16.360s 2335.080us 49 50 98.00
stress_all 49 50 98.00
keymgr_stress_all 318.740s 22275.790us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.260s 11.679us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.500s 31.212us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.620s 524.311us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.620s 524.311us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.940s 32.258us 5 5 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_csr_aliasing 15.390s 521.899us 5 5 100.00
keymgr_same_csr_outstanding 4.160s 180.196us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.940s 32.258us 5 5 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_csr_aliasing 15.390s 521.899us 5 5 100.00
keymgr_same_csr_outstanding 4.160s 180.196us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 9.470s 346.313us 20 20 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.520s 325.437us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.520s 325.437us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.520s 325.437us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.520s 325.437us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.630s 916.282us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.470s 346.313us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.520s 325.437us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 70.750s 1993.645us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_random 46.680s 2363.793us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_random 46.680s 2363.793us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 2.030s 116.766us 20 20 100.00
keymgr_random 46.680s 2363.793us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 5.860s 670.734us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 32.340s 8910.446us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 32.340s 8910.446us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 46.680s 2363.793us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 10.060s 1375.224us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 20.080s 3581.536us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 5.860s 670.734us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.080s 3581.536us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.080s 3581.536us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.080s 3581.536us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.570s 1212.222us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 20.080s 3581.536us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 32 50 64.00
keymgr_stress_all_with_rand_reset 18.860s 9729.179us 32 50 64.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 30403391026252374039644082061190511084679808708178430690306879915949245109331 1170
UVM_ERROR @ 7603721814 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 7603721814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_kmac_rsp_err 85854493485286292922393577823887983066426922552568508358728912849784442240313 139
UVM_ERROR @ 14102638 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 14102638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload_otbn 53762001998201175669311796027390314092945369713323447264899256723648636604214 89
UVM_ERROR @ 2500769 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2500769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 42774918023040592970396779454635460752825132456644355129064273428407360810232 939
UVM_ERROR @ 387297784 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 387297784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21619613883194528330932303167306381120981067931202377137439481712716036036798 193
UVM_ERROR @ 464762757 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 464762757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40828928272384302359872367444025087161905541034787210610431126123642837332394 931
UVM_ERROR @ 1743425213 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1743425213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 81807441637539710471579242688387982505734340411404957549912416737793712845851 122
UVM_ERROR @ 121099221 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 121099221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49567447179299847993729510948236868486787013297849463515307163156537826836947 1002
UVM_ERROR @ 909684822 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 909684822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19311451277129352108729220834183776407457023744747249297910301091499123294062 586
UVM_ERROR @ 175183341 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 175183341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 27200046864684064456195500605418721976594263320332891821810340600920975747251 148
UVM_ERROR @ 451132831 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 451132831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48883000339556410852675962357683834450484909033303431530426760979937952093718 561
UVM_ERROR @ 333753193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 333753193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79619086171404804116614014112426785238645152973532561539766262074413505641788 259
UVM_ERROR @ 145973195 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 145973195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45891751928564885273773366158240972923277224559874609934291724109154758295565 121
UVM_ERROR @ 114053436 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114053436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106787888080629798890951956300252007120348488521896992183278866461741170683950 405
UVM_ERROR @ 157088306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 157088306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65324012282200720401606499872263744371255230706023408273554286448970112713367 1095
UVM_ERROR @ 350541879 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 350541879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 54824613053821114637366570759669244512631817509603044887444380265488244941929 288
UVM_ERROR @ 520065188 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 520065188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46435303353192425587665408242827564874527858423183790311509443763443707269581 585
UVM_ERROR @ 156650709 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 156650709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 20422428632498349211768873842954532335664015647155477041937441218972293493815 167
UVM_ERROR @ 472971198 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 472971198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 60637772240291539751556093566957348288568659018072758581177616284951731672638 867
UVM_ERROR @ 387105404 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 387105404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 89565184547929828772022959550790613720802032178276787229751931806057211922311 704
UVM_ERROR @ 254234486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 254234486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48270442237261585229676392133407366225522430934932076546531682724794266325177 729
UVM_ERROR @ 990782925 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 990782925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 39362054521747399290115310831228788433436145975826430906342348486390975348221 166
UVM_ERROR @ 370023470 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 370023470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---