Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 86.38 %
  • assert
  • 94.13 %
  • func
  • 96.09 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.77 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.32%
V2S
100.00%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.000s 111.378us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.510s 17.527us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.430s 15.218us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.230s 83.646us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 2.060s 77.390us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.890s 31.960us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.430s 15.218us 20 20 100.00
lc_ctrl_csr_aliasing 2.060s 77.390us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.440s 151.629us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.530s 2376.848us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.200s 99.731us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.350s 91.066us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_errors 47 50 94.00
lc_ctrl_errors 15.680s 730.586us 47 50 94.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_prog_failure 4.350s 91.066us 50 50 100.00
lc_ctrl_errors 15.680s 730.586us 47 50 94.00
lc_ctrl_security_escalation 10.020s 383.603us 50 50 100.00
lc_ctrl_jtag_state_failure 84.380s 7248.540us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.750s 2361.938us 20 20 100.00
lc_ctrl_jtag_errors 47.810s 4936.641us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 9.770s 280.508us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.530s 655.525us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.750s 2361.938us 20 20 100.00
lc_ctrl_jtag_errors 47.810s 4936.641us 20 20 100.00
lc_ctrl_jtag_access 18.390s 924.428us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.240s 1265.298us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.900s 415.174us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.420s 990.517us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.550s 1335.166us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.330s 567.873us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.610s 31.468us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.980s 207.697us 10 10 100.00
lc_ctrl_jtag_alert_test 2.490s 226.402us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 27.730s 3804.735us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.420s 14.309us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 429.490s 14992.033us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.530s 69.714us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 5.500s 310.552us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 5.500s 310.552us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.510s 17.527us 5 5 100.00
lc_ctrl_csr_rw 1.430s 15.218us 20 20 100.00
lc_ctrl_csr_aliasing 2.060s 77.390us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.900s 23.913us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.510s 17.527us 5 5 100.00
lc_ctrl_csr_rw 1.430s 15.218us 20 20 100.00
lc_ctrl_csr_aliasing 2.060s 77.390us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.900s 23.913us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
lc_ctrl_tl_intg_err 3.410s 115.600us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.410s 115.600us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.530s 2376.848us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 13.240s 717.024us 50 50 100.00
lc_ctrl_sec_cm 9.120s 126.872us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.020s 383.603us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.440s 151.629us 50 50 100.00
lc_ctrl_jtag_state_post_trans 23.530s 655.525us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.650s 890.356us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.650s 890.356us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 14.650s 776.382us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.800s 833.474us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.800s 833.474us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
lc_ctrl_stress_all_with_rand_reset 166.530s 4465.854us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 22 test runs
lc_ctrl_stress_all_with_rand_reset 62188855719055539583101732579633824823339784613483915358844399165263226378485 4362
UVM_INFO @ 18666432951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18959820337623818750226549157832763194686653921098131249162497170622553015780 4696
UVM_INFO @ 2753814783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86780778599937516493466018471132285046710350252236524028617581874224111737025 5319
UVM_INFO @ 2332104177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64756220918235952556158254361415529823159241757215621550196635208940901090836 6653
UVM_INFO @ 3191127041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109261333244044148067611779439872472676278973143973276994837810573836459191417 1555
UVM_INFO @ 2590494485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62834479881877660479930534477449997307595586799754490687635482890569037292587 1890
UVM_INFO @ 2609523903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105143855721323407467842594092625711205901752707823250783382186898285909094606 1383
UVM_INFO @ 412388727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 11713519650129463019241414972400274700849811401641419382983204824953291901643 13017
UVM_INFO @ 13298360243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 4602232937448159400307392631832268648461712819144987707300779720280553941350 2987
UVM_INFO @ 5378945408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52675678112600287378545433418865854187680647723518609754200769807650986175658 9453
UVM_INFO @ 6151847217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21178262291306074879862702755866589982280370860253180898288399742043438200432 2662
UVM_INFO @ 1406484660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21792851380367271170143254025281047712139585551834710271089446528172099155394 12723
UVM_INFO @ 26743784555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95432244135883019156524005600555946428432994348364224654874765168966125542325 12603
UVM_INFO @ 2973346814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55790657190499072169066415805323840570114322838225488752421104947965302422773 3309
UVM_INFO @ 2150448882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 88542715458784296792130971244285413016258740128734530226747639181933016806593 1456
UVM_INFO @ 944939705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65813898942024739302957387356032446110152495525903405042628190110575531906837 3731
UVM_INFO @ 2515988854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51497968236627598184277448466410804585620633540225110227211686111178719492206 1059
UVM_INFO @ 4502555809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58395087493952020870023515641800712651889891607132348444830169923662009568218 1531
UVM_INFO @ 1560819365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69928343374872448517039690904546358695074648510375776646871912649052433149185 3598
UVM_INFO @ 1313626634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30073943824942555810212398984511935038722891721743189281542316110301733272703 1755
UVM_INFO @ 2984861924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26663903840801054778811819754971804162471955941456432554708085663876245854225 609
UVM_INFO @ 2062493945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25714010369754271857328872687747382931719630961868927209652672939700623877402 201
UVM_INFO @ 456442104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 5 test runs
lc_ctrl_stress_all 106045602801021985849839631917299525005421610279341791645743603975232028519202 5842
UVM_INFO @ 1213085313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 871869086738457402747146263067035374095110932816288569831758118719267070780 2084
UVM_INFO @ 12911636738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 54510757446115915632730062626753417922851731261906687457571340768674830556967 5154
UVM_INFO @ 4240119223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 23202546330058711710214813721659548594227719872660101402481878528805296623658 671
UVM_INFO @ 169888684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 111856082124369236762322874914298688289083295381666316970989213465676978648070 1256
UVM_INFO @ 105551777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:265) driver [driver] m_transaction_tasks nonempty after reset: '{*:*} 1 test run
lc_ctrl_errors 17929951165335026405416220133348135893342090319506496633600403576003124605864 548
UVM_INFO @ 30050074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 104007177341315891595121140766624902988868764657631539995480272196137192301460 8669
UVM_INFO @ 10976975747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---