Simulation Results: sysrst_ctrl

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 98.62 %
  • assert
  • 98.47 %
  • func
  • 90.34 %
  • line
  • 99.03 %
  • branch
  • 99.18 %
  • cond
  • 98.09 %
  • toggle
  • 100.00 %
  • FSM
  • 96.79 %
Validation stages
V1
100.00%
V2
98.20%
V2S
100.00%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sysrst_ctrl_smoke 8.460s 2112.282us 50 50 100.00
input_output_inverted 50 50 100.00
sysrst_ctrl_in_out_inverted 10.440s 2459.208us 50 50 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 8.900s 2401.502us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.710s 2340.651us 5 5 100.00
csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_hw_reset 20.760s 6034.399us 5 5 100.00
csr_rw 20 20 100.00
sysrst_ctrl_csr_rw 8.780s 2052.458us 20 20 100.00
csr_bit_bash 5 5 100.00
sysrst_ctrl_csr_bit_bash 224.560s 76119.511us 5 5 100.00
csr_aliasing 5 5 100.00
sysrst_ctrl_csr_aliasing 14.420s 3174.740us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 7.840s 2048.824us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sysrst_ctrl_csr_rw 8.780s 2052.458us 20 20 100.00
sysrst_ctrl_csr_aliasing 14.420s 3174.740us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 50 50 100.00
sysrst_ctrl_combo_detect 479.390s 178554.275us 50 50 100.00
combo_detect_with_pre_cond 92 100 92.00
sysrst_ctrl_combo_detect_with_pre_cond 518.830s 176796.031us 92 100 92.00
auto_block_key_outputs 50 50 100.00
sysrst_ctrl_auto_blk_key_output 528.870s 336006.005us 50 50 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 2277.110s 1426954.867us 50 50 100.00
pin_output_keyboard_inversion_control 50 50 100.00
sysrst_ctrl_pin_override_test 10.040s 2510.378us 50 50 100.00
pin_input_value_accessibility 50 50 100.00
sysrst_ctrl_pin_access_test 8.220s 2074.753us 50 50 100.00
ec_power_on_reset 49 50 98.00
sysrst_ctrl_ec_pwr_on_rst 3600.105s 0.000us 49 50 98.00
flash_write_protect_output 50 50 100.00
sysrst_ctrl_flash_wr_prot_out 10.810s 2612.023us 50 50 100.00
ultra_low_power_test 46 50 92.00
sysrst_ctrl_ultra_low_pwr 251.670s 971745.039us 46 50 92.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 56.660s 39998.255us 2 2 100.00
stress_all 50 50 100.00
sysrst_ctrl_stress_all 811.740s 305983.075us 50 50 100.00
alert_test 50 50 100.00
sysrst_ctrl_alert_test 7.810s 2012.474us 50 50 100.00
intr_test 50 50 100.00
sysrst_ctrl_intr_test 8.940s 2013.706us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sysrst_ctrl_tl_errors 9.040s 2031.092us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sysrst_ctrl_tl_errors 9.040s 2031.092us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 20.760s 6034.399us 5 5 100.00
sysrst_ctrl_csr_rw 8.780s 2052.458us 20 20 100.00
sysrst_ctrl_csr_aliasing 14.420s 3174.740us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 54.400s 10550.732us 20 20 100.00
tl_d_partial_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 20.760s 6034.399us 5 5 100.00
sysrst_ctrl_csr_rw 8.780s 2052.458us 20 20 100.00
sysrst_ctrl_csr_aliasing 14.420s 3174.740us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 54.400s 10550.732us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
sysrst_ctrl_sec_cm 97.730s 42008.264us 5 5 100.00
sysrst_ctrl_tl_intg_err 120.910s 42460.843us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
sysrst_ctrl_tl_intg_err 120.910s 42460.843us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
sysrst_ctrl_stress_all_with_rand_reset 27.220s 8062.605us 48 50 96.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  4 test runs
sysrst_ctrl_ultra_low_pwr 49527591863137331231105732564000255445160830640430315240803172294369399859476 658
UVM_ERROR @ 3168965248 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3168965248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 72238809718514930134565248787075798126112750333520875772742021308664032671783 658
UVM_INFO @ 4565110590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 4885110590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 4898444883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 55374185992423323965569369243568315349920901831355766324628778642701277493243 658
UVM_ERROR @ 394775051044 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 394775051044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 85046815324922946827575687674502192792979786074023155790428924717231690755986 659
UVM_INFO @ 8820596241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 11250596241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 11261672109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 3 test runs
sysrst_ctrl_combo_detect_with_pre_cond 5858081200841378846093787305100306716377485692257372878118799060643547943684 678
UVM_INFO @ 60203988462 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
UVM_INFO @ 60204009296 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xc1
UVM_INFO @ 64303545538 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 64303630063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
sysrst_ctrl_combo_detect_with_pre_cond 64590897426865135034137854331923444817413010467083572496259070994914536072514 671
UVM_INFO @ 13917828302 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13937828302 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_ERROR @ 14137878681 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (1 [0x1] vs 3 [0x3])
UVM_INFO @ 14137878681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
sysrst_ctrl_combo_detect_with_pre_cond 38157715853546085018245324991481442225221600454814591311018650013064491859352 693
UVM_ERROR @ 38706037816 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38706037816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
sysrst_ctrl_ec_pwr_on_rst 107037551351909873361952558895612375632335905879055272229712328377095726220503 None
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 71882174982532783648193250481159091293740580632450166758093877450846791940357 667
UVM_ERROR @ 13520092383 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
UVM_INFO @ 13520092383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) 1 test run
sysrst_ctrl_stress_all_with_rand_reset 91094281890017985643678302965288784271867394457513295902529402587856728894354 690
UVM_ERROR @ 11067495865 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11067495865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 91138322988233276246159774440958156751882019354735516439866602064260511297254 738
UVM_ERROR @ 102213266636 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 102213266636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) 1 test run
sysrst_ctrl_stress_all_with_rand_reset 33281212403885391531725223435841669322139714164129820297825680768785580904227 663
UVM_ERROR @ 4188207435 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4188207435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 22912035137448613290070791863438077216655568160802015967965305020838865698285 667
UVM_ERROR @ 12831154174 ps: (cip_base_vseq.sv:708) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12831154174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 50460437372151815306096215678355592263025344520576133231079054718970868652635 668
UVM_ERROR @ 14936283611 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 14936283611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 20168211883776127704842009706548779239569183837092933940749841993751323692296 667
UVM_ERROR @ 12710469963 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4
UVM_INFO @ 12710469963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---