| V1 |
|
100.00% |
| V2 |
|
84.86% |
| V2S |
|
100.00% |
| V3 |
|
8.00% |
| unmapped |
|
74.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 6.000s | 125.660us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 109.816us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| pattgen_csr_rw | 7.000s | 15.655us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| pattgen_csr_bit_bash | 4.000s | 192.522us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| pattgen_csr_aliasing | 2.000s | 52.819us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 8.000s | 38.323us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| pattgen_csr_rw | 7.000s | 15.655us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 52.819us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 23 | 50 | 46.00 | |||
| pattgen_perf | 3601.000s | 0.000us | 23 | 50 | 46.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 77.000s | 5177.744us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 3.000s | 87.450us | 50 | 50 | 100.00 | |
| stress_all | 21 | 50 | 42.00 | |||
| pattgen_stress_all | 10802.138s | 0.000us | 21 | 50 | 42.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| pattgen_alert_test | 3.000s | 23.113us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| pattgen_intr_test | 2.000s | 21.871us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 66.697us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 66.697us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 109.816us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 7.000s | 15.655us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 52.819us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 24.943us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 109.816us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 7.000s | 15.655us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 52.819us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 24.943us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 8.000s | 107.996us | 20 | 20 | 100.00 | |
| pattgen_sec_cm | 2.000s | 264.125us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| pattgen_tl_intg_err | 8.000s | 107.996us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 4 | 50 | 8.00 | |||
| pattgen_stress_all_with_rand_reset | 157.000s | 5395.453us | 4 | 50 | 8.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 37 | 50 | 74.00 | |||
| pattgen_inactive_level | 235.000s | 10039.998us | 37 | 50 | 74.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 44 test runs | |||
| pattgen_stress_all_with_rand_reset | 90081592504564286794782808850711888352635623665876178803285038250378923243046 | 136 |
UVM_ERROR @ 4837253205 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4837253205 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 4837853208 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 35276983835959756110236564456085601888549970441415456054126730998109346726948 | 189 |
UVM_ERROR @ 5273517044 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5273517044 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 5273928812 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 48839378229913486659675083285362342173817209834039913931578387777310727866753 | 245 |
UVM_ERROR @ 1954343852 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1954343852 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1954399408 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 47017389226609438091282583667768084762333004868469526377191853913026244364782 | 161 |
UVM_ERROR @ 5306359112 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5306359112 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 5307359114 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 111072883110145995842617475437943720592613256368384305329743874976941632602395 | 214 |
UVM_ERROR @ 17194338738 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 17194338738 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 17194755403 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 17807781109438778904515681635449226347702420272855224950394483195135565851621 | 130 |
UVM_ERROR @ 284691868 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 284691868 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 284791868 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 38250403828468685187624963519583751052653618005673561800026687062422167596272 | 233 |
UVM_ERROR @ 1061722935 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1061722935 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1061765039 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 76281927562207176972347499654054636174380189558038042047076290264780197366048 | 130 |
UVM_ERROR @ 1558811439 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1558811439 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1558903749 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 91304209950678109203146560396026706291821558758452328649330092875785048485807 | 232 |
UVM_ERROR @ 3804036299 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3804036299 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 3804082811 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 48015998190262929100075643455171813760514350575666295927231160269159006095459 | 183 |
UVM_ERROR @ 1611413820 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1611413820 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1611580484 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 101727247698917507143282490259072324557391542114908142653857822601397355921871 | 133 |
UVM_ERROR @ 1716916068 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1716916068 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1716956884 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 32987131049291147780345801693047534725322603183589367585086634333369215948721 | 338 |
UVM_ERROR @ 8511487444 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8511487444 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 8511727444 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 46019133774963257493635303128712300205570066900853629687963290802288222047948 | 117 |
UVM_ERROR @ 493769969 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 493769969 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 493791021 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 1007189346687845385117760019448519208088753184834468424748592971909398071601 | 115 |
UVM_ERROR @ 481006621 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 481006621 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 481027673 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36428319363766913239734248627332425182653592867569642666799456262679316440166 | 147 |
UVM_ERROR @ 134494663 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 134494663 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 134545168 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51795652183972163139613095427167842847241432197553214182566476568172601950801 | 121 |
UVM_ERROR @ 875730907 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 875730907 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 875812539 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 10609144267291729474070268383561629464811579198685777309702194378172805681214 | 244 |
UVM_ERROR @ 14018331224 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 14018331224 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 14018775672 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 63400379959603543845908471591084255706481754428195481046923747228181853221358 | 250 |
UVM_ERROR @ 933998471 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 933998471 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 934040139 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 56813689140736525965081749267076875123632511549101898650353280185341461686310 | 124 |
UVM_ERROR @ 2600905149 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2600905149 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2601201445 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 15131925689012004905847907990866621777366698279462431810469287095252201875090 | 113 |
UVM_ERROR @ 441732443 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 441732443 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 442132443 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 58806437807824291324945089490548047711913957360791949492491096201496339386996 | 140 |
UVM_ERROR @ 713044776 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 713044776 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 713076354 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 77886936189394607565084600626698285384417336974387253957461951403347076001113 | 120 |
UVM_ERROR @ 1212812447 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1212812447 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1213145783 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 101520854336999456659808644261352080914282608430294595143999074423014394416461 | 113 |
UVM_ERROR @ 240989830 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 240989830 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 241185481 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 49508382193199110836549209758765677886983323212596980223939635520837158112286 | 123 |
UVM_ERROR @ 903849932 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 903849932 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 903899932 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 5013246512050891970964704707039999359380690559226125701117858593559121083074 | 115 |
UVM_ERROR @ 2078907348 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2078907348 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2079067348 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 100304198532814251981329400437558891619245561009104218901937743769067699093899 | 195 |
UVM_ERROR @ 754719420 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 754719420 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 754802756 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 61285956679364796171592571578699394831573308481480729877509303198996422175380 | 226 |
UVM_ERROR @ 9369168511 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9369168511 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 9369368511 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 79732961979512762045296430686313632201230520408244317074578514048880096744593 | 239 |
UVM_ERROR @ 8162824399 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8162824399 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 8163236167 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 63700927131966723597543970522440871735240815211905632456664311743029075678602 | 124 |
UVM_ERROR @ 2321316566 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2321316566 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2321733236 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 69403486943077965354079179978854395111137063974447775781953569465256575169914 | 131 |
UVM_ERROR @ 773666098 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 773666098 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 773697025 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 3336961203046189022234439442770459379209770676748376645219617652144263906458 | 113 |
UVM_ERROR @ 108709036 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 108709036 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 108761121 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84710478034712801687819290473000555765683785283165900132906519051070265310087 | 304 |
UVM_ERROR @ 2329920365 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2329920365 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 2330025625 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93636755230658533433822119941925177700948548075429232319902827826714922442659 | 119 |
UVM_ERROR @ 3728563304 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3728563304 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3728683304 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 85865598753873771981423672856917308271005606464425742343064586275323754049794 | 161 |
UVM_ERROR @ 776677516 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 776677516 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 776780606 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 107589869354154855265811857324161466466314536370796528430123704757801144945916 | 391 |
UVM_ERROR @ 4330758645 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4330758645 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 4330865025 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 50642207549331449169348330325131122844740545161385371720171832080748889270321 | 327 |
UVM_ERROR @ 1218907238 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1218907238 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 1218977238 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 34413023864103618997208695071411444583357273784353389124544616544368843624771 | 237 |
UVM_ERROR @ 7906246720 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7906246720 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 7906538389 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 107726328932918503301922372568111454824160151905424819706084470591655424556215 | 113 |
UVM_ERROR @ 113030156 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 113030156 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 113101584 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51348247006045988859210981651327628750450177842917608657248799046047848249062 | 140 |
UVM_ERROR @ 7772211007 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7772211007 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 7773336007 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31915427206502025791867487066176858225166442199251748894766720862510594993097 | 124 |
UVM_ERROR @ 1538954427 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1538954427 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1539146737 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 27055373130655786262795328452432999645033508228506229941967230400766698939939 | 113 |
UVM_ERROR @ 449473043 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 449473043 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 449681378 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 107354723710886048970805774338773623462091121243479563689063673984509617708890 | 121 |
UVM_ERROR @ 1528569157 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1528569157 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1528650789 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 64814600451594656953719817452662475705777148062403429951980118869108820066844 | 312 |
UVM_ERROR @ 4743513205 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4743513205 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 4743679869 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 92419832014326554956293823299538418809019881383882966617769353095398571767737 | 126 |
UVM_ERROR @ 451807076 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 451807076 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 451837688 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| Job timed out after * minutes | 24 test runs | |||
| pattgen_perf | 30158642806199826019004144901320143569291465912295063888234183455376161031255 | None | ||
| pattgen_stress_all | 46338419348400068112564106534297812426368401884796808575438251052668607122211 | None | ||
| pattgen_stress_all | 60191363295066186036433745219813809791859634346208216498861851188033539705190 | None | ||
| pattgen_perf | 47797645464613375375857928641093840538397563579151267813547593048866413291976 | None | ||
| pattgen_perf | 104120626405368722841967739723435089434659341009638281429397417638180559976636 | None | ||
| pattgen_stress_all | 90285981344130261727305758934879106041613052368995547493472946939372345976153 | None | ||
| pattgen_stress_all | 85549500709732908395934944504168472517844732966088716923863080124728888200009 | None | ||
| pattgen_stress_all | 80052149055786218684833087482229970663939882130407994157595360354483172371488 | None | ||
| pattgen_perf | 115756733591958260732730093795954434937902491066214443610810506063193216312361 | None | ||
| pattgen_stress_all | 87027358824014226816284344961044052606196948443100970977453383669105731285408 | None | ||
| pattgen_perf | 107581369993006852549882101937519457528407276416872671904651407682942734346372 | None | ||
| pattgen_perf | 73733775560500791097696911659143239614521397174953942685372151258792130441129 | None | ||
| pattgen_perf | 61970987880500944361145582515314356375531230479392339901433948306802481473323 | None | ||
| pattgen_stress_all | 32733228480448405530996656748398617209281988751710038608908797781355320857459 | None | ||
| pattgen_perf | 55702402983946472249947859944720395448418991236498252932555402502673207716795 | None | ||
| pattgen_perf | 19362695909577089037047494325262616208804533979398078826737062815721464185649 | None | ||
| pattgen_stress_all | 27745729437005656321218921416046678656464401364507320422845759789432522814596 | None | ||
| pattgen_perf | 76373833293546509067673112581123489515176139961524277830004729732561225374729 | None | ||
| pattgen_perf | 108794512436739553479028585250376175330875590795071535945897945776556368212697 | None | ||
| pattgen_stress_all | 30006573568062117285502321650230911343124998250479608894099844511545655352584 | None | ||
| pattgen_perf | 106933884909270017658253398474685216049189876106553660757073681793617635376520 | None | ||
| pattgen_perf | 38933583884700159236504911040795009440100447905827848789845242015928788468693 | None | ||
| pattgen_perf | 98033244198754240674505144131396980074151907696048937550081083888086833234177 | None | ||
| pattgen_perf | 33536052785440378072096950551056927772406787895969225902884496897289809905992 | None | ||
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 19 test runs | |||
| pattgen_stress_all | 9290369287730020262124474724195880506791750682241706578658005774693565638577 | 145 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11312
|
|
| pattgen_stress_all | 69683769214933540020150431939186286459291609618197150927739743448312285028003 | 156 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11352
|
|
| pattgen_stress_all | 44777953153205644839991344999376631175779627277654058370254868842294311896877 | 146 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11318
|
|
| pattgen_stress_all | 11255505279348586170425565947248540606158496308729736588580690674590612042599 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11265
|
|
| pattgen_stress_all | 39804998362978254194283610470274765418921532060579857483583364170719134896212 | 160 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11486
|
|
| pattgen_stress_all | 43442426311641123142813220151654496096605668385825008513919514774242537920084 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11315
|
|
| pattgen_stress_all | 45562959884053207431737896449399681631229860808555346329565189909748876730218 | 140 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11336
|
|
| pattgen_stress_all | 56802283862099972557711751290099053839618865568079989460583165702382677561130 | 148 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11267
|
|
| pattgen_stress_all | 5053867776149741109129812767961389360377867633846842748418428187867750112186 | 148 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11322
|
|
| pattgen_stress_all | 81662932082177250094921334582200957994412006097248686217482382978733353103891 | 145 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11364
|
|
| pattgen_stress_all | 34294984290891580830963137197934130168400462027348029636791601451748402795298 | 133 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11362
|
|
| pattgen_stress_all | 83899147186738324789284494720450646775308332364310796443177518476818713999596 | 142 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11299
|
|
| pattgen_stress_all | 100259475829669011141554733117955097373127234658502662262829021888552638435571 | 146 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @16110
|
|
| pattgen_stress_all | 534039723852615636889366863975011650525619714128931843863588657236590449475 | 140 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11312
|
|
| pattgen_stress_all | 11257518474463687553735729740864965192730168409030452939749467921370010956967 | 162 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11307
|
|
| pattgen_stress_all | 25063735085801305773613799941482535321121798222678845885591079599235331168793 | 151 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11296
|
|
| pattgen_stress_all | 97413836824598740979089433592119664230250672271186966016017331067732646599888 | 149 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11347
|
|
| pattgen_stress_all | 57508389647951307989370643226744050996715267965185229993321299149905984221138 | 140 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11338
|
|
| pattgen_stress_all | 54475615548090050378187438267775515403329818089256248142848737620419894963805 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11326
|
|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 13 test runs | |||
| pattgen_perf | 82299480572350802435151459222138835933808857500862277041054632051619710640356 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_stress_all | 96062907366384950801596554804654564696542306023723638769459989402544548120915 | 136 |
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 73536730348220436287195740562121108948009872031132264881290727539758934722794 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 50074956338765206359282427133945607522398365280920180011605781153165680370165 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 25298249432090899982229127049000505942878294922571365041653211241510718884637 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 87974452708272469898126257450761409390163028441171097906505232506751393569910 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 37781863453228333394254630254660961085328137004587170396699239577317116880708 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 12248666156291758808155712152019089881095155888831213252665714632181330793148 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 31684024804247211909409659885467138331157366277883241913358622498578853124327 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 54702416543696176608271549304572385592977021814607631647245720765422113406650 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 45905632199203188889425803379109919935349585551440691565580831446459410130384 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 100240814141012759796612959439889222907901017124278652713551242747065263965100 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113346931655370408387346822797424483294331497146482026031514539978550766823135 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) | 3 test runs | |||
| pattgen_inactive_level | 46787411136451135418218189855940992170118822425449977917023163558567604659454 | 99 |
UVM_INFO @ 10006590487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 10587447501539300878893241509867109479386380960446267283654437367878332678856 | 99 |
UVM_INFO @ 10013133971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 83144438943200987876351237556140990640551824365853184246915999711500457545833 | 99 |
UVM_INFO @ 10041116361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 2 test runs | |||
| pattgen_stress_all_with_rand_reset | 86040570059090482933945531881065764977684085696145125865038291743158129868803 | 131 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| pattgen_stress_all_with_rand_reset | 7741225344209263305438840317975618271874193643863202631280003167616598402516 | 125 |
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | 2 test runs | |||
| pattgen_inactive_level | 44336910583510273928111128955154768506068930262620554171048348987315611783090 | 99 |
UVM_INFO @ 10067976787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 106578622127466386385083496262575283000611106708724981228869531479584181285795 | 99 |
UVM_INFO @ 10029450859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) | 1 test run | |||
| pattgen_inactive_level | 105841738821014516416095834826710872172081998173386132234103153443317677048699 | 99 |
UVM_INFO @ 10003671014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) | 1 test run | |||
| pattgen_inactive_level | 12581364760935739865997286277581043719085304665181287395057660527064925976116 | 99 |
UVM_INFO @ 10075356526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) | 1 test run | |||
| pattgen_inactive_level | 62559092425846343564600203660171029316698338659178760076961681713604339214858 | 99 |
UVM_INFO @ 10007191511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) | 1 test run | |||
| pattgen_inactive_level | 72908259520243992272920024398332259922778431134827309116044768450375853510491 | 99 |
UVM_INFO @ 10017528043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) | 1 test run | |||
| pattgen_inactive_level | 101510407093270488343144164384136006490340840838467622113989966328929041138131 | 99 |
UVM_INFO @ 10039997817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | 1 test run | |||
| pattgen_inactive_level | 30252885739280758506419916380806334706382556222145626003656614809033327804118 | 99 |
UVM_INFO @ 10276945327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | 1 test run | |||
| pattgen_inactive_level | 86752947530332142752944677272661446789963990338011439927399874331441981008673 | 99 |
UVM_INFO @ 10011418978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 1 test run | |||
| pattgen_inactive_level | 64130950822226535997139947338415798941860267125619090653019059145233137090587 | 99 |
UVM_INFO @ 10002237587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|