Simulation Results: sram_ctrl/ret

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.24 %
  • code
  • 83.49 %
  • assert
  • 96.43 %
  • func
  • 96.80 %
  • block
  • 94.01 %
  • line
  • 95.19 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
95.71%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 133.962us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 52.236us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 21.000s 11.848us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 190.946us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 14.422us 5 5 100.00
csr_mem_rw_with_rand_reset 17 20 85.00
sram_ctrl_csr_mem_rw_with_rand_reset 22.000s 63.352us 17 20 85.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 21.000s 11.848us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.422us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 14.000s 2624.769us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 1405.654us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 11.000s 3553.745us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 258.000s 15447.647us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 10.000s 1865.915us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 22.000s 772.280us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 9.000s 518.788us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 14.000s 996.620us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 112.172us 5 5 100.00
sram_ctrl_partial_access_b2b 326.000s 35544.985us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 56.823us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 39.559us 5 5 100.00
sram_ctrl_throughput_w_readback 3.000s 42.739us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 15.000s 813.805us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 26.763us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 53.000s 10793.134us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 21.000s 27.561us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 24.000s 507.585us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 24.000s 507.585us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 52.236us 5 5 100.00
sram_ctrl_csr_rw 21.000s 11.848us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.422us 5 5 100.00
sram_ctrl_same_csr_outstanding 21.000s 55.803us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 52.236us 5 5 100.00
sram_ctrl_csr_rw 21.000s 11.848us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.422us 5 5 100.00
sram_ctrl_same_csr_outstanding 21.000s 55.803us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 1629.612us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
sram_ctrl_tl_intg_err 23.000s 631.589us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 23.000s 631.589us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 15.000s 813.805us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 15.000s 813.805us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 21.000s 11.848us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 14.000s 996.620us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 996.620us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 996.620us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 9.000s 518.788us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 62.859us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 1629.612us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 40.227us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 133.962us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 133.962us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 14.000s 996.620us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 9.000s 518.788us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 133.962us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 482.278us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 105.000s 2597.878us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 83970131303893086029090148680422849643527378664831677808229990653904899836970 88
UVM_INFO @ 88631760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 26882475463103859417643946534245635404981694001534963806680609577988990915769 94
UVM_INFO @ 63352097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 55068377292336546914148819606242179080309919325206690039437542759198631182933 94
UVM_INFO @ 34291162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---