Simulation Results

Simulation Results: sysrst_ctrl

16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.31 %

code
98.65 %

assert
98.37 %

func
91.92 %

line
99.48 %

branch
99.56 %

cond
98.04 %

toggle
100.00 %

FSM
96.15 %

Validation stages

V1		100.00%
V2		97.78%
V2S		100.00%
V3		96.00%

165/165 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sysrst_ctrl_smoke	9.300s	2113.688us	50	50	100.00
input_output_inverted				50	50	100.00
	sysrst_ctrl_in_out_inverted	11.080s	2448.924us	50	50	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	7.390s	2437.780us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	9.250s	2295.283us	5	5	100.00
csr_hw_reset				5	5	100.00
	sysrst_ctrl_csr_hw_reset	13.770s	4029.117us	5	5	100.00
csr_rw				20	20	100.00
	sysrst_ctrl_csr_rw	9.090s	2060.823us	20	20	100.00
csr_bit_bash				5	5	100.00
	sysrst_ctrl_csr_bit_bash	180.480s	52524.733us	5	5	100.00
csr_aliasing				5	5	100.00
	sysrst_ctrl_csr_aliasing	9.070s	2613.424us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	8.920s	2089.366us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sysrst_ctrl_csr_rw	9.090s	2060.823us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.070s	2613.424us	5	5	100.00

706/722 passed

97.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				50	50	100.00
	sysrst_ctrl_combo_detect	414.060s	145990.536us	50	50	100.00
combo_detect_with_pre_cond				90	100	90.00
	sysrst_ctrl_combo_detect_with_pre_cond	365.730s	137818.570us	90	100	90.00
auto_block_key_outputs				50	50	100.00
	sysrst_ctrl_auto_blk_key_output	755.550s	318764.208us	50	50	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	2591.290s	1687031.532us	50	50	100.00
pin_output_keyboard_inversion_control				50	50	100.00
	sysrst_ctrl_pin_override_test	11.090s	2507.990us	50	50	100.00
pin_input_value_accessibility				50	50	100.00
	sysrst_ctrl_pin_access_test	8.890s	2023.466us	50	50	100.00
ec_power_on_reset				48	50	96.00
	sysrst_ctrl_ec_pwr_on_rst	196.320s	180862.445us	48	50	96.00
flash_write_protect_output				50	50	100.00
	sysrst_ctrl_flash_wr_prot_out	11.120s	2607.931us	50	50	100.00
ultra_low_power_test				48	50	96.00
	sysrst_ctrl_ultra_low_pwr	413.400s	1715222.640us	48	50	96.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	46.830s	34848.696us	2	2	100.00
stress_all				48	50	96.00
	sysrst_ctrl_stress_all	469.220s	139250.585us	48	50	96.00
alert_test				50	50	100.00
	sysrst_ctrl_alert_test	8.160s	2010.726us	50	50	100.00
intr_test				50	50	100.00
	sysrst_ctrl_intr_test	7.900s	2009.943us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.230s	2048.986us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.230s	2048.986us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	13.770s	4029.117us	5	5	100.00
	sysrst_ctrl_csr_rw	9.090s	2060.823us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.070s	2613.424us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	22.290s	5197.526us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	13.770s	4029.117us	5	5	100.00
	sysrst_ctrl_csr_rw	9.090s	2060.823us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.070s	2613.424us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	22.290s	5197.526us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	sysrst_ctrl_sec_cm	94.740s	42010.444us	5	5	100.00
	sysrst_ctrl_tl_intg_err	123.930s	42478.219us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	sysrst_ctrl_tl_intg_err	123.930s	42478.219us	20	20	100.00

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				48	50	96.00
	sysrst_ctrl_stress_all_with_rand_reset	23.030s	22686.513us	48	50	96.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				5 test runs
	sysrst_ctrl_ultra_low_pwr	58073148248517172441314122731601127888806988803324166465321039562762419143452	657	UVM_ERROR @ 4858214789 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 4858214789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all_with_rand_reset	82606708024036939372260499029162215535144101590313913497260155158987704419711	731	UVM_INFO @ 14636132160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 17811132160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 17829809336 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq UVM_INFO @ 19826192936 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq
	sysrst_ctrl_stress_all	99495800926112634740755120875339084748546309303118685717277444593927582843016	660	UVM_INFO @ 7005651347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 9245651347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 9279927118 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_edge_detect_vseq UVM_INFO @ 11275877503 ps: (sysrst_ctrl_edge_detect_vseq.sv:141) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Starting the body from edge_detect_vseq
	sysrst_ctrl_stress_all	75947782674720122640338089327150217531698193343799310063285517932774456809950	658	UVM_INFO @ 4549825371 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 7334935754 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 7365769334 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq UVM_INFO @ 9364993661 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:106) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Starting the body from ultra_low_pwr_vseq
	sysrst_ctrl_ultra_low_pwr	69473487459622522372193033293217921399254330474323119836219949399290520145823	657	UVM_INFO @ 2163126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 5128126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 6163126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 10503126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				4 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	110393192347460444260526860594571018498136848519198327670051899610672494944564	690	UVM_ERROR @ 35909977361 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 35909977361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	105063915598416150203694043560331363872538941332343388621502034650852137652112	665	UVM_ERROR @ 13803513400 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 13803513400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	39710360970189443115414178275751812578691185019425579982747099781770525122384	707	UVM_ERROR @ 115867074054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 115867074054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	27052261497898121410726359007734045854830124772346580981956128624160538019352	691	UVM_ERROR @ 38243804579 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 38243804579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *				3 test runs
	sysrst_ctrl_ec_pwr_on_rst	5494099966872817153195808554150762918284899267545487809302016230446758373799	657	UVM_INFO @ 2519511631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all_with_rand_reset	43932284016282659765761038049040786371397692587192348900668382198818268865561	678	UVM_INFO @ 10989644107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ec_pwr_on_rst	25042888832596275902002792614282255394657863003215489667963421196041697248317	657	UVM_INFO @ 2276033987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				3 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	44076664032702627488483876526503355903095802761393474288503527385673965299396	719	UVM_ERROR @ 68631856163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 68631856163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	63195137361364008701796169187932179013183540427865999344600896304021465600071	722	UVM_ERROR @ 98105733100 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 98105733100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	48359114482571422286692148365052676362772470048931171153469176393144551797004	683	UVM_ERROR @ 31288305469 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 31288305469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	88996132197905333792568198942613955920328539061858498186884786020541333861873	667	UVM_INFO @ 23490770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0 UVM_INFO @ 24620770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 24640770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 34667540336 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xe6
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	94892712165571456403905959099211046486750796452894355737860477235369014696861	694	UVM_ERROR @ 35296770591 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o UVM_INFO @ 35296770591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	8716363181777686638035053636216771364244331445757753557896508339935949911781	697	UVM_INFO @ 38806424952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 38826424952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_ERROR @ 38951447872 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4]) UVM_INFO @ 38951447872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]