Simulation Results: sram_ctrl/ret

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.79 %
  • code
  • 83.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 111.982us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 33.732us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.225us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 766.710us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.233us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 49.397us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 18.225us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 25.233us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 15.000s 3395.957us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 361.307us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 17.000s 4171.651us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 210.000s 15946.847us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 11.000s 6905.188us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 20.000s 1072.341us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2324.387us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 1396.678us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 57.255us 8 8 100.00
sram_ctrl_partial_access_b2b 361.000s 46082.420us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 102.950us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 100.527us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 117.764us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 15.000s 14244.584us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 81.823us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 74.000s 49549.199us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 34.830us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 449.207us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 449.207us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 33.732us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.225us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 25.233us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.292us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 33.732us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.225us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 25.233us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.292us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 788.563us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 2103.774us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 2103.774us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 14244.584us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 14244.584us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.225us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1396.678us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1396.678us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1396.678us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2324.387us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 34.828us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 788.563us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 69.036us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 111.982us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 111.982us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 1396.678us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2324.387us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 111.982us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 529.063us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 112.000s 3462.031us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 63803121882890155517864216672680342318202330388243171759005553389204028030460 86
UVM_INFO @ 44301451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 95631051142375352136487562555188138510036785043872637951824982448472283002542 86
UVM_INFO @ 100237341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 9883753616064402746963945582933467268934530850088339486914544379569412321902 86
UVM_INFO @ 102949749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 45821559119126535771506854849037489305915131619466007782702516142547631886941 86
UVM_INFO @ 100526581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 114538400847964957607671981783664944147689382653798546669078713552564499016176 86
UVM_INFO @ 103339603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47031704101538984715259402801182650572703767562410627744382279944861527799778 86
UVM_INFO @ 49941330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 55873932794729289859777795300134724528155223101358696888016635699437303752705 86
UVM_INFO @ 25683254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 103825327831936470591038130643015174929126454317498503402025394034266120826778 86
UVM_INFO @ 30953324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 112531640208086156701836581642039933434161249829330102059195890566065836519343 86
UVM_INFO @ 151840323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 32952706775164254269327395572528076249150236692373044466005616230546549575527 86
UVM_INFO @ 51858112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 71252795614539449681179433154164986186705424989100774107343583654134451988535 86
UVM_INFO @ 28313887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 5804323482994187245415982986287935629161655250421201937235763205793122240175 86
UVM_INFO @ 79676189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 21263599710698092925378214529184548591915525554975793718050198439644134250952 86
UVM_INFO @ 59518052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 27649556644775651843289058142708960643882263709387429173553294799848973651285 86
UVM_INFO @ 99439453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 76826734547507766574566929714154759174002585836036610038438123014657839949674 86
UVM_INFO @ 142749343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 82758135514258147176185817976833784247472547833554137812993384927679368682065 86
UVM_INFO @ 66724723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 115226252176584639502856933994344675866713008212209229929198053974197080638611 86
UVM_INFO @ 221467823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 5629951315829157046845219981600544663878435988960715731357631371805934518356 86
UVM_INFO @ 117763895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 4148913851182023335605219863953019783729220153698063458671625180709591552155 86
UVM_INFO @ 212472551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 8542859427532879244425582692050009701107252739413047561929685775593547446894 86
UVM_INFO @ 120006664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67312775890727189302040795226884397736487059721345408922728941008362827541305 86
UVM_INFO @ 31011231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 70968188991835504158238017746033124300695245532184168711757567429115174123693 86
UVM_INFO @ 59874480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 65199749256454662121690734177238115458666089785505281805585722008381168268027 86
UVM_INFO @ 104329679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104778524281481903870041191174710832311604187671253835086312921670085831466223 86
UVM_INFO @ 118306760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---