Simulation Results

Simulation Results: otbn

27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.30 %

code
82.67 %

assert
97.23 %

func
100.00 %

block
97.82 %

line
98.00 %

branch
82.51 %

toggle
82.55 %

FSM
67.61 %

Validation stages

V1		100.00%
V2		98.16%
V2S		96.96%
V3		30.00%
unmapped		100.00%

116/116 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	23.000s	154.221us	1	1	100.00
single_binary				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	32.000s	89.000us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	32.000s	27.993us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	36.000s	1075.765us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	32.000s	35.038us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	34.000s	224.469us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	32.000s	27.993us	5	5	100.00
	otbn_csr_aliasing	32.000s	35.038us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	113.000s	30846.679us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	59.000s	3963.093us	1	1	100.00

160/163 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	65.000s	372.907us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	84.000s	2141.349us	1	1	100.00
back_to_back				9	10	90.00
	otbn_multi	106.000s	781.113us	9	10	90.00
stress_all				9	10	90.00
	otbn_stress_all	518.000s	1529.680us	9	10	90.00
lc_escalation				59	60	98.33
	otbn_escalate	34.000s	33.421us	59	60	98.33
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	10.000s	103.407us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	22.000s	54.141us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	33.000s	47.172us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	32.000s	194.768us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	15.000s	34.512us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	15.000s	34.512us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	32.000s	89.000us	1	1	100.00
	otbn_csr_rw	32.000s	27.993us	5	5	100.00
	otbn_csr_aliasing	32.000s	35.038us	1	1	100.00
	otbn_same_csr_outstanding	30.000s	37.026us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	32.000s	89.000us	1	1	100.00
	otbn_csr_rw	32.000s	27.993us	5	5	100.00
	otbn_csr_aliasing	32.000s	35.038us	1	1	100.00
	otbn_same_csr_outstanding	30.000s	37.026us	5	5	100.00

V2S

319/329 passed

96.96 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				24	25	96.00
	otbn_imem_err	41.000s	47.822us	10	10	100.00
	otbn_dmem_err	31.000s	173.291us	14	15	93.33
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	37.000s	345.973us	4	5	80.00
	otbn_controller_ispr_rdata_err	35.000s	19.783us	5	5	100.00
	otbn_mac_bignum_acc_err	35.000s	96.601us	5	5	100.00
	otbn_urnd_err	11.000s	63.008us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	32.000s	10.772us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	33.000s	27.586us	2	2	100.00
otbn_non_sec_partial_wipe				10	10	100.00
	otbn_partial_wipe	31.000s	52.845us	10	10	100.00
tl_intg_err				26	30	86.67
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
	otbn_tl_intg_err	43.000s	231.245us	25	25	100.00
passthru_mem_tl_intg_err				5	5	100.00
	otbn_passthru_mem_tl_intg_err	95.000s	226.332us	5	5	100.00
prim_fsm_check				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
prim_count_check				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	23.000s	154.221us	1	1	100.00
sec_cm_data_mem_integrity				14	15	93.33
	otbn_dmem_err	31.000s	173.291us	14	15	93.33
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	41.000s	47.822us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	43.000s	231.245us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	34.000s	33.421us	59	60	98.33
sec_cm_controller_fsm_local_esc				35	40	87.50
	otbn_imem_err	41.000s	47.822us	10	10	100.00
	otbn_dmem_err	31.000s	173.291us	14	15	93.33
	otbn_zero_state_err_urnd	10.000s	103.407us	5	5	100.00
	otbn_illegal_mem_acc	32.000s	10.772us	5	5	100.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_controller_fsm_sparse				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_scramble_key_sideload				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_scramble_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	41.000s	47.822us	10	10	100.00
	otbn_dmem_err	31.000s	173.291us	14	15	93.33
	otbn_zero_state_err_urnd	10.000s	103.407us	5	5	100.00
	otbn_illegal_mem_acc	32.000s	10.772us	5	5	100.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_scramble_ctrl_fsm_sparse				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	34.000s	33.421us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	41.000s	47.822us	10	10	100.00
	otbn_dmem_err	31.000s	173.291us	14	15	93.33
	otbn_zero_state_err_urnd	10.000s	103.407us	5	5	100.00
	otbn_illegal_mem_acc	32.000s	10.772us	5	5	100.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_start_stop_ctrl_fsm_sparse				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_data_reg_sw_sca				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	35.000s	35.341us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	32.000s	42.443us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	87.000s	1851.136us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	87.000s	1851.136us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				9	10	90.00
	otbn_rf_base_intg_err	34.000s	25.705us	9	10	90.00
sec_cm_rf_base_data_reg_sw_glitch_detect				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_stack_wr_ptr_ctr_redun				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_rf_bignum_data_reg_sw_integrity				9	10	90.00
	otbn_rf_bignum_intg_err	52.000s	569.737us	9	10	90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_loop_stack_ctr_redun				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	63.574us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	63.574us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	26.000s	17.494us	7	7	100.00
sec_cm_data_mem_sec_wipe				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_instruction_mem_sec_wipe				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_data_reg_sw_sec_wipe				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_write_mem_integrity				9	10	90.00
	otbn_multi	106.000s	781.113us	9	10	90.00
sec_cm_ctrl_flow_count				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_ctrl_flow_sca				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	29.000s	57.416us	5	5	100.00
sec_cm_key_sideload				100	100	100.00
	otbn_single	55.000s	174.660us	100	100	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	otbn_sec_cm	419.000s	3069.456us	1	5	20.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	otbn_stress_all_with_rand_reset	314.000s	913.337us	3	10	30.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	20.000s	21.454us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				5 test runs
	otbn_alu_bignum_mod_err	39737542784131573124154957774702280899100339829701531661445248173719994478291	115	UVM_INFO @ 345973204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all	57230067682476897381671718723698275942869910883549975036434388366558388181925	146	UVM_INFO @ 46208608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_base_intg_err	53268418389878117305266182010165711782550120187731369679842948055264341903821	122	UVM_INFO @ 356818743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	13402788143245915571921543536739337457433447353428239805921843470180049567931	111	UVM_INFO @ 37232276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	31800225945331815340009805951880770489402404590678534770141526991905883185320	110	UVM_INFO @ 1278895767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed				4 test runs
	otbn_sec_cm	9329533277980730326840846002970580223911891224440637374229179516853301130635	90	UVM_ERROR @ 8255372 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 8255372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	39484504398772988017906368472129965894158778029930131599980994493760533081843	126	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 417209132 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed UVM_ERROR @ 417209132 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 417209132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	27703269483604315537448408480939886229312014873880039146256335472805995949653	85	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 5023584 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed UVM_ERROR @ 5023584 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 5023584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	35131778609087927149898612765054089995131695637647094599793201142225817522572	117	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 206600543 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed UVM_ERROR @ 206600543 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 206600543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	otbn_stress_all_with_rand_reset	12211815749301759248389008526660205705337795090076576561548036516440078052132	183	UVM_INFO @ 377855185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	17484199231087391137162711669566084147906841785631386759125123428311644871208	329	UVM_INFO @ 16740320998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	93341789364009585433538505161461258391248443717115563262376213338803681948909	176	UVM_INFO @ 286297334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	44955961005046056217922933375617370110936538227068942486939390237242886971150	352	UVM_INFO @ 913337130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				2 test runs
	otbn_stress_all_with_rand_reset	70932197082544883381566651854399734177593633122783115726903567479146386205916	183	UVM_INFO @ 927279500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	70125425213927902198137527487773448194489644504275153748226301912872867607914	178	UVM_INFO @ 497706525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS)				1 test run
	otbn_dmem_err	112719786619517556572121097953191359957226549819949742859914712953425252975632	112	UVM_ERROR @ 12938537 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A UVM_INFO @ 12938537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	109266758869656175421188809053279133000184457779489990860113272317880935769059	246	UVM_INFO @ 5826145500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				1 test run
	otbn_multi	113461007308543147956875177655699294768609528831026580744170685683479575112935	150	UVM_INFO @ 95334781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---