Simulation Results: uart

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.17 %
  • code
  • 96.86 %
  • assert
  • 98.27 %
  • func
  • 99.37 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
96.98%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 19.430s 5826.485us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.070s 1067.595us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.950s 18.171us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.740s 272.232us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.020s 41.336us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.560s 97.971us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.950s 18.171us 5 5 100.00
uart_csr_aliasing 1.020s 41.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 209.710s 104537.123us 10 10 100.00
parity 20 20 100.00
uart_smoke 19.430s 5826.485us 10 10 100.00
uart_tx_rx 209.710s 104537.123us 10 10 100.00
parity_error 20 20 100.00
uart_intr 380.260s 319681.187us 10 10 100.00
uart_rx_parity_err 171.440s 164177.558us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 209.710s 104537.123us 10 10 100.00
uart_intr 380.260s 319681.187us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 216.970s 224504.089us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 139.900s 104652.388us 10 10 100.00
fifo_reset 199 200 99.50
uart_fifo_reset 417.610s 148321.647us 199 200 99.50
rx_frame_err 10 10 100.00
uart_intr 380.260s 319681.187us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 380.260s 319681.187us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 380.260s 319681.187us 10 10 100.00
perf 10 10 100.00
uart_perf 527.470s 17610.958us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 18.640s 9149.429us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 18.640s 9149.429us 10 10 100.00
rx_noise_filter 1 10 10.00
uart_noise_filter 164.950s 102160.353us 1 10 10.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 40.600s 43333.093us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 19.090s 7259.054us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 26.660s 4229.922us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 1011.560s 141577.717us 10 10 100.00
stress_all 8 10 80.00
uart_stress_all 977.510s 261513.413us 8 10 80.00
alert_test 10 10 100.00
uart_alert_test 0.910s 26.584us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.950s 29.666us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.940s 501.229us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.940s 501.229us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 1.070s 1067.595us 1 1 100.00
uart_csr_rw 0.950s 18.171us 5 5 100.00
uart_csr_aliasing 1.020s 41.336us 1 1 100.00
uart_same_csr_outstanding 1.150s 161.437us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 1.070s 1067.595us 1 1 100.00
uart_csr_rw 0.950s 18.171us 5 5 100.00
uart_csr_aliasing 1.020s 41.336us 1 1 100.00
uart_same_csr_outstanding 1.150s 161.437us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.260s 83.581us 5 5 100.00
uart_tl_intg_err 1.810s 378.645us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.810s 378.645us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 82.070s 12545.157us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 5 test runs
uart_noise_filter 51967180107187277393615569145064879551067113856215236797714588961081800885400 75
UVM_ERROR @ 737469061 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 743162893 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 748122037 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 750887321 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 63418394291300469465214191928548853819932197565234228266175386785397898465471 81
UVM_ERROR @ 63142488877 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 63143561013 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 63148839221 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 63151591724 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 79471116484378454045800947160051610882062001183010944445411639704305515422353 75
UVM_ERROR @ 9436093103 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 9436093103 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9445926397 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 9445926397 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 35772324531324304035021419651554782427238093348440479462885579219902990766165 79
UVM_ERROR @ 8205911846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8216711846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8440431846 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 8440431846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 69016409882996737395981745840032034414661404995673699053860913892853088715223 158
UVM_ERROR @ 1737025654 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_INFO @ 1769821310 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/836
UVM_ERROR @ 1785943630 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1801861870 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 3 test runs
uart_noise_filter 36002053630536737009223403571499627750546301790773597353750095485005002385720 76
UVM_ERROR @ 6054971520 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6054971520 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 6063991520 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 9
UVM_ERROR @ 6064031520 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 27231345950538103612938508458115212551772534797322789983980810821258855524662 82
UVM_ERROR @ 71812372469 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 71812372469 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 72191316677 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 72191316677 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_noise_filter 30095872628468735423159234684227637512239796831026420665228697135240844289597 76
UVM_ERROR @ 18629514316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18629514316 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 19133234316 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (146 [0x92] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_INFO @ 19133294316 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/8
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 3 test runs
uart_stress_all 37834620826752698816807412477156419366375469266920090039751915923097845859110 140
UVM_ERROR @ 253782133051 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 253782175155 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 253834047283 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 253834047283 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 68734853479046713205360203905396577919739831166847275947885561944300726727629 76
UVM_ERROR @ 10129734686 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10131534686 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (56 [0x38] vs 249 [0xf9]) reg name: uart_reg_block.rdata
UVM_ERROR @ 10131934686 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10133334686 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (56 [0x38] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 58075812954067085984792451769441397425560089463417787572862872898351743694760 75
UVM_ERROR @ 2361053025 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2361063442 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (131 [0x83] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2361084276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2361188446 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (131 [0x83] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 2 test runs
uart_stress_all_with_rand_reset 104391777726335491994674291352476289842158748778435986487886394932560530779578 117
UVM_INFO @ 1113763411 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/165
UVM_INFO @ 1168525580 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/165
UVM_INFO @ 1218370925 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/165
UVM_INFO @ 1285435571 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/165
uart_fifo_reset 51923900926518127561810413808953817887592438375339368015619631593392069579565 74
UVM_INFO @ 2166290663 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
UVM_INFO @ 4827292561 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
UVM_INFO @ 4891111616 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
UVM_INFO @ 5740448074 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 68182630217896814937981757596389235827573892138875488510577369186341610007058 74
UVM_ERROR @ 190477379 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 381807651 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 381807651 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 474285338 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1