Simulation Results: sram_ctrl/ret

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
94.59%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 404.745us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 26.819us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.620us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 57.920us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.961us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
sram_ctrl_csr_mem_rw_with_rand_reset 7.000s 10093.339us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 14.620us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.961us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 13.000s 1439.535us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 197.048us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 17.000s 1373.509us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 163.000s 11486.067us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 10.000s 1551.570us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 24.000s 4128.124us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 8.000s 590.402us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 17.000s 7538.810us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 60.592us 8 8 100.00
sram_ctrl_partial_access_b2b 417.000s 268113.941us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 52.872us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 131.751us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 30.982us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 12.000s 444.715us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 207.798us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 45.000s 17353.486us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 12.973us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 562.128us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 562.128us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 26.819us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.620us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.961us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.012us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 26.819us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.620us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.961us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.012us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 464.985us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 765.206us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 765.206us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 12.000s 444.715us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 12.000s 444.715us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.620us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 17.000s 7538.810us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 17.000s 7538.810us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 17.000s 7538.810us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 8.000s 590.402us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 55.471us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 464.985us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 39.676us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 404.745us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 404.745us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 17.000s 7538.810us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 8.000s 590.402us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 404.745us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 379.635us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 117.000s 2662.482us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 62305340684536549246823761116958484226879496770062212216005136132194080820367 86
UVM_INFO @ 28679449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 110922229293760911945770464083319666535397178969688793652527919704562132187421 86
UVM_INFO @ 131750580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 24146158499534292972447427138728446829818973980406886484875273273857477611601 86
UVM_INFO @ 52872227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 60321207691915997033972788740504527877735027152773884098635954474977407718073 86
UVM_INFO @ 103952061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 99283501865076320405144427155050773388773247669733505044460998579517610472186 86
UVM_INFO @ 55198775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54608342469806598831224823166454773343184894569448842703658924346287964557793 86
UVM_INFO @ 108686148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 36304489642966366236833578336649204142550419074408698052593695793283228485343 86
UVM_INFO @ 50898212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 16589874413503757856471382728779424762396249516284965794421707033519364922073 86
UVM_INFO @ 113537515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62691950253324433463925708026290076984253238795601356849316391453870761646303 86
UVM_INFO @ 54229404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 70952194192569995503065269384991700148379326428970575049704527060661767524387 86
UVM_INFO @ 100238302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 68390325097747919445945990178263510376261505795316272648209176556362175117813 86
UVM_INFO @ 492208867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 59325757135258204844348678752559000338855456206346415773314103910000267421355 86
UVM_INFO @ 48044802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 6691225920647974997541523547591289461116152878288152935193474126874122508607 86
UVM_INFO @ 101681518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 75650243039687202728775141562461897914898359531947332308972121873980279094509 86
UVM_INFO @ 91764830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 30414786957168491499909434631289732963222813140105639896539698044311285196171 86
UVM_INFO @ 104635413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 92406858685789587782872745324063908651207277553383894653893624614916727944099 86
UVM_INFO @ 58945932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 14343276459540748175439192859889419875494846847265300862208819365537412158913 86
UVM_INFO @ 30982263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 57915625069975691663896643552759736870458371286797985079676025941020482173053 86
UVM_INFO @ 32447559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 92986575367399489054610745633567359870283773075201881277680851518417724556151 86
UVM_INFO @ 114268778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 56661626568809603886050350002260300350354136109084235967038834023775412035895 86
UVM_INFO @ 41018197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 33528100798458418320054285128888178743971207277030965296332082311212728955960 86
UVM_INFO @ 116809060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 102414671737919916340646607481278302341533288454560524549303393522423634269426 86
UVM_INFO @ 29063474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 47769482186934538904509547255327621964303256538512667758253694286642404919635 86
UVM_INFO @ 130272133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 85561186198038312040177651226541775570984264942496742746494612178877964710634 86
UVM_INFO @ 55395297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 32845245809910091631322305587641821749996611925199774414025961054680353515597 88
UVM_INFO @ 467431060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [sram_ctrl_common_vseq] wait timeout occurred! 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 92684500229395406098449625429370833381581595562687894569553995154994039094342 98
UVM_INFO @ 10093339218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---