Simulation Results: sram_ctrl/main

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.90 %
  • code
  • 95.94 %
  • assert
  • 97.96 %
  • func
  • 96.80 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 1416.375us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.622us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 13.576us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 62.292us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 30.220us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 5800.755us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 13.576us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 30.220us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 308.000s 257399.936us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 123.000s 6050.042us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 54.000s 68211.824us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 218.000s 5133.133us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 200.000s 79503.823us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 101.000s 100190.175us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 59.000s 19700.212us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 58.000s 83568.760us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 9.000s 14023.669us 8 8 100.00
sram_ctrl_partial_access_b2b 328.000s 21720.645us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 732.885us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 2641.134us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 2669.294us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 21.000s 4829.501us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 350.031us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 433.000s 415119.832us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 27.325us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 678.630us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 678.630us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.622us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.576us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 30.220us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 40.382us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.622us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.576us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 30.220us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 40.382us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7433.410us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1167.267us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1167.267us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 21.000s 4829.501us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 21.000s 4829.501us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 13.576us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 58.000s 83568.760us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 58.000s 83568.760us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 58.000s 83568.760us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 59.000s 19700.212us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 1341.282us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7433.410us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 8.000s 8344.784us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 1416.375us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 1416.375us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 58.000s 83568.760us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 59.000s 19700.212us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 1416.375us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1252.809us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 72.000s 25734.225us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 9886433628417918014347772898996528428497481152310710840833277667660267381579 86
UVM_INFO @ 732884767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 101824826137652520551630916380428999831631923002165229459769312187986892983500 86
UVM_INFO @ 662020343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 72883103273758053270253313226912258965247601906741879702341479179511959690517 86
UVM_INFO @ 3298970709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 75934986848235382318368243765793132152133598239082771330016852302913780538502 86
UVM_INFO @ 2641134000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 90575237921254324630475080109558244109440214317599381305881861389809708074778 86
UVM_INFO @ 675679041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 73562678569333091926233873412452248144926257084523125242487590652428852181165 86
UVM_INFO @ 2881130066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 4440973081420465496092281302972880829441951997794603853521422563446046280179 86
UVM_INFO @ 1319959036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 53234958296400367235289973636467895651936487236163261447016654136999141092706 86
UVM_INFO @ 7344721722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 55075567748693063544900036416223712190377927951356466866722055589065636795092 86
UVM_INFO @ 687316750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 70746809569195048264688221503675306753539624828406284862731551374431042416131 86
UVM_INFO @ 664555075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 17592549344200720663824456684902976242611107252345661167089188057971891010804 86
UVM_INFO @ 660742862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 45173272267401295605276311416645206228018597385196661349592059584251813835778 86
UVM_INFO @ 2639826435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 28084530245555286448121388026444764108941982604315239605510636761701809669480 86
UVM_INFO @ 2639524289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 95292481387845470684070498616855660448526383536679009850323172743375199359204 86
UVM_INFO @ 2751827153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 12902237325649723610779044767846286493872532355478180529489028633855656122831 86
UVM_INFO @ 2627058981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 58266274043591710052141470057866403975471578946592526446227597303565173396111 86
UVM_INFO @ 704120796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 42170926877084346471350335641323139543963065744106853681333145291603229483981 86
UVM_INFO @ 2669293948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 99955341625776522412488256506387617262232802489591564936743903953159598646689 86
UVM_INFO @ 1332808094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 5873079685305369220386206478841778122337129762218379969299785594007377383882 86
UVM_INFO @ 683077366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67515464516693943200099204992046720905151374198203122725896524122493901482135 86
UVM_INFO @ 2768089618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 109409343100119007845350511412437339691864048232244467516592172528166322624324 86
UVM_INFO @ 691829326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 50937570611688370874633499854357004188439547136272710102531491986888284260611 86
UVM_INFO @ 2652772072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 72274071280259201882642341704518457253577942313218418519504613375085794233869 86
UVM_INFO @ 699408908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 14712408328129135706605108259147505558918929420115358612570509895541979174684 86
UVM_INFO @ 2764811604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---