Simulation Results: sysrst_ctrl

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 97.78 %
  • assert
  • 98.47 %
  • func
  • 90.57 %
  • line
  • 98.92 %
  • branch
  • 99.00 %
  • cond
  • 98.01 %
  • toggle
  • 100.00 %
  • FSM
  • 92.95 %
Validation stages
V1
97.67%
V2
94.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 7.280s 2112.542us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 7.400s 2460.079us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 7.460s 2154.220us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 4 5 80.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.340s 2520.653us 4 5 80.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 5.160s 6055.006us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 7.260s 2034.859us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 88.040s 39056.852us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 8.190s 3180.487us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 7.440s 2050.376us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 7.260s 2034.859us 5 5 100.00
sysrst_ctrl_csr_aliasing 8.190s 3180.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 312.540s 157560.433us 25 25 100.00
combo_detect_with_pre_cond 87 100 87.00
sysrst_ctrl_combo_detect_with_pre_cond 382.220s 174052.852us 87 100 87.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 208.890s 109154.728us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 551.100s 930891.152us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 8.090s 2513.853us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 7.290s 2248.171us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 10.830s 4819.722us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 9.290s 2610.428us 10 10 100.00
ultra_low_power_test 22 25 88.00
sysrst_ctrl_ultra_low_pwr 685.750s 4883221.482us 22 25 88.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 87.060s 35092.649us 2 2 100.00
stress_all 9 10 90.00
sysrst_ctrl_stress_all 136.830s 72725.419us 9 10 90.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 4.770s 2014.695us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 7.440s 2010.088us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 8.580s 2041.747us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 8.580s 2041.747us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 5.160s 6055.006us 1 1 100.00
sysrst_ctrl_csr_rw 7.260s 2034.859us 5 5 100.00
sysrst_ctrl_csr_aliasing 8.190s 3180.487us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.310s 4840.914us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 5.160s 6055.006us 1 1 100.00
sysrst_ctrl_csr_rw 7.260s 2034.859us 5 5 100.00
sysrst_ctrl_csr_aliasing 8.190s 3180.487us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.310s 4840.914us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 80.490s 42010.943us 5 5 100.00
sysrst_ctrl_tl_intg_err 102.120s 42378.413us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 102.120s 42378.413us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 14.180s 4705.683us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 5 test runs
sysrst_ctrl_combo_detect_with_pre_cond 100298746620692904425867979309969464864658480676271924134390061527973671473926 724
UVM_ERROR @ 77403548900 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 77403548900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 90690511911555267842825044703438540142514753458423300248646649369332646298209 716
UVM_ERROR @ 66024294851 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66024294851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 69776266329176396231955965142686557419086863710488568812858647473114752693649 710
UVM_INFO @ 63539292721 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 63559292721 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 73721602409 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x21
UVM_INFO @ 73721855033 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x21
sysrst_ctrl_combo_detect_with_pre_cond 12930717018555794865632628622300111425459146537813065257624188586171555142756 676
UVM_ERROR @ 26249867344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26249867344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 84698459973937875750736755302580827774150438654030226521753670253702180176333 704
UVM_ERROR @ 85799277665 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 85799277665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  4 test runs
sysrst_ctrl_stress_all 20940243554513867011640658364277660178213463938886633415739810555580375536235 666
UVM_INFO @ 10694489571 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 11784489571 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 11791696699 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq
UVM_INFO @ 13789636699 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:76) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Starting the body from auto_blk_key_output_vseq
sysrst_ctrl_ultra_low_pwr 32134866855914496708692223158321660377911623448782012385457760302094628750703 655
UVM_INFO @ 2484225259 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 6384225259 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 6420857540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 57242765326778230706669160738935024780989141505544138045713577557965960902400 655
UVM_INFO @ 2405339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 4965339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 7495339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 10395339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
sysrst_ctrl_ultra_low_pwr 114270592287210281477953757890458852348174852423559997309015924412828379840302 656
UVM_INFO @ 5661374427 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 6306374427 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 6322214335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 3 test runs
sysrst_ctrl_combo_detect_with_pre_cond 52735912541919501314060222802423432562020810112621083194433280901140673977309 757
UVM_INFO @ 120953903350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x18
UVM_INFO @ 120953933350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x19
UVM_INFO @ 121398393350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 121413282202 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 17
sysrst_ctrl_combo_detect_with_pre_cond 44106757701270445342764158741304307985804779082948551324019477626464970800268 700
UVM_ERROR @ 51377776581 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51377776581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 28579720877585915390680928364818060944020337701001665125700598986136258965489 686
UVM_ERROR @ 63329488381 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 63329488381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 2 test runs
sysrst_ctrl_combo_detect_with_pre_cond 77189910904508313456082326140822667811517257436812748971896522808219070848475 707
UVM_ERROR @ 56816789612 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
UVM_INFO @ 56816789612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 99170544889853410243967077572035652954839864203460047610049872556453094489766 663
UVM_ERROR @ 13805872215 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
UVM_INFO @ 13805872215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * 1 test run
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 23902220935526262293899646827292195591628604500568567393896109371417124091948 657
UVM_INFO @ 2507308492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 83695195611180923247551630378977931579011001867515439449074255877413996097243 671
UVM_INFO @ 17585509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 17790509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 17810509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 19950509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:139) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] pulse_width_l = 45
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 101673275770188270271844164512800275146805814496998732892980804352555342091556 663
UVM_ERROR @ 14346075102 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 14346075102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 101106611428592982726569851612505563723863727694577688892127938104767083966711 694
UVM_ERROR @ 17883732835 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
UVM_INFO @ 17883732835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---