Simulation Results: otbn

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.31 %
  • code
  • 82.70 %
  • assert
  • 97.23 %
  • func
  • 100.00 %
  • block
  • 97.86 %
  • line
  • 98.04 %
  • branch
  • 82.67 %
  • toggle
  • 82.50 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
99.39%
V2S
99.09%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 43.000s 48.350us 1 1 100.00
single_binary 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 38.000s 58.675us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 36.000s 16.354us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 39.000s 295.866us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 65.035us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 41.000s 239.081us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 36.000s 16.354us 5 5 100.00
otbn_csr_aliasing 37.000s 65.035us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 112.000s 6208.417us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 56.000s 1247.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 70.000s 111.428us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 86.000s 190.601us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 137.000s 476.971us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 147.000s 5237.276us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 67.000s 211.493us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 13.000s 16.310us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 50.000s 1035.035us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 39.000s 24.712us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 37.000s 32.571us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 22.000s 334.280us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 22.000s 334.280us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 38.000s 58.675us 1 1 100.00
otbn_csr_rw 36.000s 16.354us 5 5 100.00
otbn_csr_aliasing 37.000s 65.035us 1 1 100.00
otbn_same_csr_outstanding 37.000s 68.697us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 38.000s 58.675us 1 1 100.00
otbn_csr_rw 36.000s 16.354us 5 5 100.00
otbn_csr_aliasing 37.000s 65.035us 1 1 100.00
otbn_same_csr_outstanding 37.000s 68.697us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 38.000s 44.079us 10 10 100.00
otbn_dmem_err 42.000s 93.687us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 41.000s 26.580us 5 5 100.00
otbn_controller_ispr_rdata_err 37.000s 18.659us 5 5 100.00
otbn_mac_bignum_acc_err 44.000s 64.569us 5 5 100.00
otbn_urnd_err 18.000s 95.403us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 36.000s 27.764us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 39.000s 31.764us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 38.000s 34.617us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
otbn_tl_intg_err 36.000s 189.988us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 87.000s 335.296us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 43.000s 48.350us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 42.000s 93.687us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 38.000s 44.079us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 36.000s 189.988us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 67.000s 211.493us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 44.079us 10 10 100.00
otbn_dmem_err 42.000s 93.687us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 16.310us 5 5 100.00
otbn_illegal_mem_acc 36.000s 27.764us 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 44.079us 10 10 100.00
otbn_dmem_err 42.000s 93.687us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 16.310us 5 5 100.00
otbn_illegal_mem_acc 36.000s 27.764us 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 67.000s 211.493us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 44.079us 10 10 100.00
otbn_dmem_err 42.000s 93.687us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 16.310us 5 5 100.00
otbn_illegal_mem_acc 36.000s 27.764us 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 38.000s 18.846us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 38.000s 56.343us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 82.000s 378.737us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 82.000s 378.737us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 43.000s 43.317us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 41.000s 57.546us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 36.000s 25.211us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 36.000s 25.211us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 38.000s 21.416us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 137.000s 476.971us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 43.000s 105.091us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 41.000s 19.532us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 481.000s 7065.166us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 339.000s 1214.854us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 41.000s 32.454us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 18293722917246303094771037295543434986956693893731800912306882362147914337832 233
UVM_INFO @ 326711449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 52803705731113005354842132778617544451805293735902344372657910945986833531058 155
UVM_INFO @ 120142416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 13524961077783416416602333216935185148972911628223261931555011037207349970552 388
UVM_INFO @ 1214854080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 56585279100996868750210936317241013813480864172764914860314722134030331935453 228
UVM_INFO @ 1106967196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 2 test runs
otbn_escalate 58312391082353724705718084073448044516630721616633095943460505689281895129490 135
UVM_INFO @ 3809121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 59154644524655867359932194259867538355742812571754260356337612259959060448162 114
UVM_INFO @ 3600607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
otbn_stress_all_with_rand_reset 12646816793191080559332180526414710717817863284265248807104641809550046734377 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_stress_all_with_rand_reset 69181940124676584827927000345354563548035706761107029975435547852199482974493 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 77682606230352009011445091040017333529347718789343694673741802542255531774596 117
UVM_INFO @ 64137304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 13420102779045678900383150595817116762603003718060640814031843676341155711760 197
UVM_INFO @ 3517282417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 91875446195364579270940490381218340602255787317384413870931796073548713285668 162
UVM_INFO @ 28066335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---