Simulation Results: sram_ctrl/ret

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.51 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 92.504us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 25.411us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 46.729us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 119.177us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.491us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 38.695us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 46.729us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 13.491us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 13.000s 736.542us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 218.451us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 10.000s 2798.852us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 209.000s 7886.512us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 485.075us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 22.000s 677.464us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 1699.945us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 1051.459us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 280.473us 8 8 100.00
sram_ctrl_partial_access_b2b 441.000s 112738.470us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 177.539us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 114.969us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 220.896us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1112.207us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 31.447us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 61.000s 8485.915us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 18.596us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 558.995us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 558.995us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 25.411us 1 1 100.00
sram_ctrl_csr_rw 2.000s 46.729us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 13.491us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 55.326us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 25.411us 1 1 100.00
sram_ctrl_csr_rw 2.000s 46.729us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 13.491us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 55.326us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2088.926us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 212.426us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 212.426us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1112.207us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1112.207us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 46.729us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1051.459us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1051.459us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1051.459us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 1699.945us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 95.100us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2088.926us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 120.861us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 92.504us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 92.504us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 1051.459us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 1699.945us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 92.504us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1828.232us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 105.000s 10420.482us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 113631541155612796661443451820768811138262435013046108396397988341792256941489 86
UVM_INFO @ 243906850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 59450150998895095067659877192417381806278362661740174120922944293857491860682 86
UVM_INFO @ 114969407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 75983058186841140501794265297754980419880844579850388811970235165624899140287 86
UVM_INFO @ 177538593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 77918817400589922202206786368264780837140825714013155308026653340000857768645 86
UVM_INFO @ 27388906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 8707459816549972639721340701291066264414222163185602680985532795171096702964 86
UVM_INFO @ 91114547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 63093810266013686453038389875710699235789736074758532755601007855303068419678 86
UVM_INFO @ 25896114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 10718469700275169219481085715317919255465650695784296699131905418242309392030 86
UVM_INFO @ 119232805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 66401502523638148516773958453040612276909402998911106035452524446280634695794 86
UVM_INFO @ 105561720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 93341389578468227416035094355803725754330486517033980626576291552747683714772 86
UVM_INFO @ 34203640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 55627241445857082248154283412480692300191227991765154221745875312964095675623 86
UVM_INFO @ 78941530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 76563276247875264238145511515132162644440759498587087550652703140824977291148 86
UVM_INFO @ 28068935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 23162786555434152679213499153433421263107699613151225260486760019281757940439 86
UVM_INFO @ 27451542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109376257637166027106530771387530903302675813957779514855141725099550173988567 86
UVM_INFO @ 102299458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 52791839497070491932869124721444155074828896709745940901002800199574570609660 86
UVM_INFO @ 52701770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 40177429530200983891840807268012511046823837686947016948072100255601319552198 86
UVM_INFO @ 95488256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 36910157947614024416710655524568119062559810422967342505561285688573053900494 86
UVM_INFO @ 220861666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 21601354361065351724793202479582998449957069494214257503302112545032747063192 86
UVM_INFO @ 220895897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 79132760470220623036887533175835430381267603324424680088314565328358608890211 86
UVM_INFO @ 30209198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25105680850018330347405174110297093543601271330395106186940858857095015733634 86
UVM_INFO @ 30236466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104559073613837902989024485866008656287743796197151707548264395323664141378644 86
UVM_INFO @ 41172912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 12514749947877464270452291110567680904990334235149112096597050372300301017242 86
UVM_INFO @ 115802922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94891528127676975404972007513835260936928275397192354354445095630001467829639 86
UVM_INFO @ 67991112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 78254124063164444674053935605970055272044037138712734504255427558235457126492 86
UVM_INFO @ 31469467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 33476346292286895550884622989073106705462128326081349230222396828039934341228 86
UVM_INFO @ 31864093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 45827622251876258088942779158678359480180198831152731875391242568102721361025 94
UVM_INFO @ 390038623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 59690373853735140750057560596707718636432829140559847643027055613486098529489 170
UVM_INFO @ 121840832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---