Simulation Results: chip

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.35 %
  • code
  • 82.81 %
  • assert
  • 97.87 %
  • func
  • 99.38 %
  • line
  • 94.47 %
  • branch
  • 94.48 %
  • cond
  • 92.91 %
  • toggle
  • 75.07 %
  • FSM
  • 57.14 %
Validation stages
V1
96.88%
V2
88.14%
V2S
100.00%
V3
81.13%
unmapped
54.84%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 226.820s 3841.076us 3 3 100.00
chip_sw_example_rom 156.750s 2843.136us 3 3 100.00
chip_sw_example_manufacturer 236.500s 3743.239us 3 3 100.00
chip_sw_example_concurrency 275.440s 3326.054us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 399.670s 6918.693us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 663.300s 5932.251us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 1209.680s 11493.503us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 7715.860s 41993.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 5 20.00
chip_csr_mem_rw_with_rand_reset 513.360s 6868.410us 1 5 20.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
chip_csr_aliasing 7715.860s 41993.896us 1 1 100.00
chip_csr_rw 663.300s 5932.251us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 10.800s 226.598us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 470.460s 5236.910us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 470.460s 5236.910us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 470.460s 5236.910us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 528.130s 4816.301us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 528.130s 4816.301us 5 5 100.00
chip_sw_uart_tx_rx_idx1 530.130s 4500.662us 5 5 100.00
chip_sw_uart_tx_rx_idx2 589.470s 4874.678us 5 5 100.00
chip_sw_uart_tx_rx_idx3 598.560s 5713.667us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2489.040s 13764.727us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2408.700s 14840.506us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1423.220s 13539.532us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 357.280s 6360.156us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 357.280s 6360.156us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 382.410s 4446.051us 3 3 100.00
chip_sw_sleep_pin_wake 1 3 33.33
chip_sw_sleep_pin_wake 305.790s 4026.204us 1 3 33.33
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 353.320s 4078.718us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1736.040s 18820.885us 5 5 100.00
chip_tap_straps_testunlock0 462.140s 6841.427us 5 5 100.00
chip_tap_straps_rma 585.070s 9448.788us 5 5 100.00
chip_tap_straps_prod 1080.560s 13050.988us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 714.200s 8049.209us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 714.200s 8049.209us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1009.780s 9339.907us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 2142.760s 16842.816us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 475.480s 4419.261us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 783.460s 6580.162us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5343.690s 20888.887us 3 3 100.00
chip_sw_aes_enc_jitter_en 268.050s 4407.153us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1207.390s 9781.176us 3 3 100.00
chip_sw_hmac_enc_jitter_en 310.130s 3945.242us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2419.470s 13943.614us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.250s 4116.148us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 567.990s 7007.181us 3 3 100.00
chip_sw_clkmgr_jitter 254.740s 2818.713us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 304.340s 3798.307us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 8 8 100.00
chip_sw_sensor_ctrl_alert 726.190s 7080.895us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 378.150s 5983.583us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 276.980s 3231.290us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 378.150s 5983.583us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 223.720s 3432.486us 3 3 100.00
chip_sw_aes_smoketest 325.150s 3253.243us 3 3 100.00
chip_sw_aon_timer_smoketest 302.100s 3518.364us 3 3 100.00
chip_sw_clkmgr_smoketest 251.430s 3809.479us 3 3 100.00
chip_sw_csrng_smoketest 277.940s 3193.689us 3 3 100.00
chip_sw_entropy_src_smoketest 1285.620s 8104.117us 3 3 100.00
chip_sw_gpio_smoketest 324.910s 3957.791us 3 3 100.00
chip_sw_hmac_smoketest 278.790s 4477.600us 3 3 100.00
chip_sw_kmac_smoketest 312.500s 3291.301us 3 3 100.00
chip_sw_otbn_smoketest 2128.570s 11163.225us 3 3 100.00
chip_sw_pwrmgr_smoketest 452.470s 7668.749us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 407.040s 7158.351us 3 3 100.00
chip_sw_rv_plic_smoketest 280.260s 3602.891us 3 3 100.00
chip_sw_rv_timer_smoketest 273.270s 3852.036us 3 3 100.00
chip_sw_rstmgr_smoketest 280.640s 3759.911us 3 3 100.00
chip_sw_sram_ctrl_smoketest 257.310s 3585.352us 3 3 100.00
chip_sw_uart_smoketest 322.630s 3573.409us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 315.990s 4204.171us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 567.550s 5982.732us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12850.310s 62172.313us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 4103.090s 15112.807us 3 3 100.00
chip_sw_rom_raw_unlock 3 3 100.00
rom_raw_unlock 313.950s 7911.600us 3 3 100.00
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 1593.020s 15561.998us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 1168.240s 14979.920us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 11039.780s 53864.593us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 11273.860s 55883.356us 3 3 100.00
tl_d_oob_addr_access 3 30 10.00
chip_tl_errors 324.740s 4890.434us 3 30 10.00
tl_d_illegal_access 3 30 10.00
chip_tl_errors 324.740s 4890.434us 3 30 10.00
tl_d_outstanding_access 12 12 100.00
chip_csr_aliasing 7715.860s 41993.896us 1 1 100.00
chip_same_csr_outstanding 4404.020s 28498.617us 5 5 100.00
chip_csr_hw_reset 399.670s 6918.693us 1 1 100.00
chip_csr_rw 663.300s 5932.251us 5 5 100.00
tl_d_partial_access 12 12 100.00
chip_csr_aliasing 7715.860s 41993.896us 1 1 100.00
chip_same_csr_outstanding 4404.020s 28498.617us 5 5 100.00
chip_csr_hw_reset 399.670s 6918.693us 1 1 100.00
chip_csr_rw 663.300s 5932.251us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 92.090s 2337.745us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 7.270s 52.773us 50 50 100.00
xbar_smoke_large_delays 95.950s 9548.696us 50 50 100.00
xbar_smoke_slow_rsp 96.800s 7503.032us 50 50 100.00
xbar_random_zero_delays 47.340s 508.159us 50 50 100.00
xbar_random_large_delays 433.370s 54366.480us 50 50 100.00
xbar_random_slow_rsp 408.150s 32427.068us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 58.860s 1267.998us 50 50 100.00
xbar_error_and_unmapped_addr 55.890s 1240.442us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 75.920s 2081.328us 50 50 100.00
xbar_error_and_unmapped_addr 55.890s 1240.442us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 104.900s 2506.587us 50 50 100.00
xbar_access_same_device_slow_rsp 895.850s 80310.990us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 78.090s 2484.277us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 559.400s 17497.941us 50 50 100.00
xbar_stress_all_with_error 606.770s 18556.969us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 653.400s 15738.766us 50 50 100.00
xbar_stress_all_with_reset_error 769.480s 22180.076us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 4103.090s 15112.807us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3738.670s 33329.291us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 4041.760s 17175.796us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 3222.520s 11651.705us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3897.860s 15619.611us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 4003.920s 16462.411us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3836.650s 15912.397us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 4192.520s 17491.149us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 3128.070s 12073.567us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 4014.230s 19237.173us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 4247.420s 16553.234us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 4022.300s 16800.286us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 4151.230s 15932.606us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 5636.440s 18952.403us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6970.510s 25395.322us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 7270.810s 24104.630us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 7132.230s 25043.932us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 6923.760s 23157.541us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 5591.250s 18329.460us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 7071.520s 23426.566us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6689.460s 23057.370us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 6744.050s 30622.744us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 6614.070s 22687.799us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 3213.510s 12429.770us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3814.150s 14973.869us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3907.010s 15634.611us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3775.300s 14606.623us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3808.410s 15247.188us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3315.100s 13546.801us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3788.550s 15520.975us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3536.000s 15577.122us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3885.440s 17488.970us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3807.490s 14694.567us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 3298.850s 13175.987us 3 3 100.00
rom_e2e_asm_init_dev 4350.780s 15357.880us 3 3 100.00
rom_e2e_asm_init_prod 4415.840s 16620.936us 3 3 100.00
rom_e2e_asm_init_prod_end 4413.300s 17672.582us 3 3 100.00
rom_e2e_asm_init_rma 4452.710s 19011.016us 3 3 100.00
rom_e2e_keymgr_init 7 9 77.78
rom_e2e_keymgr_init_rom_ext_meas 8186.250s 30793.763us 1 3 33.33
rom_e2e_keymgr_init_rom_ext_no_meas 8388.530s 29218.524us 3 3 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 8418.540s 30488.897us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 4349.620s 17068.980us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.178s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.178s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 317.350s 3598.965us 3 3 100.00
chip_sw_aes_enc_jitter_en 268.050s 4407.153us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 196.470s 3584.516us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 276.370s 3708.388us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 1894.620s 12315.489us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 275.360s 4278.346us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 523.490s 6147.108us 3 3 100.00
chip_sw_all_escalation_resets 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 711.060s 5695.603us 3 3 100.00
chip_plic_all_irqs_10 386.650s 3853.354us 3 3 100.00
chip_plic_all_irqs_20 517.030s 5629.657us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 322.330s 4574.146us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1668.790s 16397.693us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 555.920s 7520.837us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 294.570s 3349.863us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.207s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1366.830s 8922.430us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1292.410s 8083.811us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1138.410s 8344.234us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 2 3 66.67
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.184s 0.000us 2 3 66.67
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 373.110s 4262.007us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 452.470s 7668.749us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 373.110s 4262.007us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 641.900s 8785.513us 0 3 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 641.900s 8785.513us 0 3 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 510.180s 9683.228us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 562.790s 6001.795us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 876.560s 6291.789us 3 3 100.00
chip_sw_aes_idle 276.370s 3708.388us 3 3 100.00
chip_sw_hmac_enc_idle 308.940s 4098.068us 3 3 100.00
chip_sw_kmac_idle 200.510s 3824.086us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 421.390s 7109.322us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 515.070s 5904.331us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 440.660s 6192.010us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 428.070s 6085.329us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1315.790s 14915.273us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 598.740s 5364.309us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 559.550s 5819.945us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 606.330s 4960.908us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 513.350s 5867.481us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 542.950s 4797.053us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 569.160s 5456.565us 3 3 100.00
chip_sw_ast_clk_outputs 1009.780s 9339.907us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 836.990s 16613.663us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 606.330s 4960.908us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 513.350s 5867.481us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 475.480s 4419.261us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 783.460s 6580.162us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5343.690s 20888.887us 3 3 100.00
chip_sw_aes_enc_jitter_en 268.050s 4407.153us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1207.390s 9781.176us 3 3 100.00
chip_sw_hmac_enc_jitter_en 310.130s 3945.242us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2419.470s 13943.614us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.250s 4116.148us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 567.990s 7007.181us 3 3 100.00
chip_sw_clkmgr_jitter 254.740s 2818.713us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 281.830s 4233.545us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 559.520s 5681.659us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 839.030s 6871.205us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 5415.920s 25895.493us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 259.410s 3395.305us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 243.220s 3480.151us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1660.750s 13280.017us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 305.680s 3964.935us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 665.110s 6474.186us 3 3 100.00
chip_sw_flash_init_reduced_freq 1984.080s 33379.864us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4070.600s 23221.624us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1009.780s 9339.907us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 562.280s 5281.322us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 432.230s 4605.907us 3 3 100.00
chip_sw_clkmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1366.830s 8922.430us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 2877.310s 24217.846us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 2 3 66.67
chip_sw_csrng_fuse_en_sw_app_read_test 419.230s 6577.932us 2 3 66.67
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 791.080s 8266.255us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 293.660s 3492.542us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 9039.480s 35280.592us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 244.920s 3175.889us 3 3 100.00
chip_sw_edn_entropy_reqs 1193.380s 9083.480us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 244.920s 3175.889us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 2877.310s 24217.846us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 288.230s 4045.543us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1958.640s 30657.556us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 730.280s 6608.737us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 783.460s 6580.162us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 515.860s 5362.526us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 475.480s 4419.261us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4863.010s 46126.826us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1958.640s 30657.556us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 318.250s 4274.597us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4863.010s 46126.826us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_lc_escalate_en 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 741.640s 12717.219us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 789.640s 6639.033us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 611.980s 5886.122us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 611.980s 5886.122us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 282.460s 4221.114us 3 3 100.00
chip_sw_hmac_enc_jitter_en 310.130s 3945.242us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 308.940s 4098.068us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2101.180s 11067.424us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 2277.900s 12018.350us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 603.160s 6148.333us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 599.510s 5406.814us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 619.530s 5013.440us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 472.180s 4265.087us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2419.470s 13943.614us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 2061.310s 12973.329us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 1894.620s 12315.489us 3 3 100.00
chip_sw_keymgr_sideload_otbn 0 3 0.00
chip_sw_keymgr_sideload_otbn 6529.820s 20018.539us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 275.850s 4218.548us 3 3 100.00
chip_sw_kmac_mode_kmac 262.770s 2954.134us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.250s 4116.148us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 237.670s 3670.744us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1951.930s 11328.208us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 200.510s 3824.086us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 523.490s 6147.108us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1736.040s 18820.885us 5 5 100.00
chip_tap_straps_rma 585.070s 9448.788us 5 5 100.00
chip_tap_straps_prod 1080.560s 13050.988us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 315.340s 4097.949us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 1226.530s 10304.347us 3 3 100.00
chip_sw_lc_ctrl_broadcast 76 84 90.48
chip_sw_flash_ctrl_lc_rw_en 322.380s 4193.040us 0 3 0.00
chip_sw_flash_rma_unlocked 4863.010s 46126.826us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 310.590s 3572.455us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 903.590s 9580.203us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 836.940s 6763.472us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 771.410s 9881.693us 0 3 0.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 553.110s 9359.613us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1038.600s 13290.250us 3 3 100.00
chip_prim_tl_access 741.640s 12717.219us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 836.990s 16613.663us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 598.740s 5364.309us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 559.550s 5819.945us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 606.330s 4960.908us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 513.350s 5867.481us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 542.950s 4797.053us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 569.160s 5456.565us 3 3 100.00
chip_tap_straps_dev 1736.040s 18820.885us 5 5 100.00
chip_tap_straps_rma 585.070s 9448.788us 5 5 100.00
chip_tap_straps_prod 1080.560s 13050.988us 5 5 100.00
chip_rv_dm_lc_disabled 575.270s 14720.753us 1 3 33.33
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 215.740s 3096.775us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 160.120s 4015.287us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 149.310s 3029.232us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 291.120s 4219.152us 3 3 100.00
chip_lc_test_locked 3 6 50.00
chip_sw_lc_walkthrough_testunlocks 2947.110s 46793.776us 2 3 66.67
chip_rv_dm_lc_disabled 575.270s 14720.753us 1 3 33.33
chip_sw_lc_walkthrough 5 15 33.33
chip_sw_lc_walkthrough_dev 1082.180s 12338.269us 0 3 0.00
chip_sw_lc_walkthrough_prod 1130.720s 14162.945us 0 3 0.00
chip_sw_lc_walkthrough_prodend 963.560s 13878.066us 3 3 100.00
chip_sw_lc_walkthrough_rma 599.210s 9400.445us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 2947.110s 46793.776us 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 8 9 88.89
chip_sw_lc_ctrl_volatile_raw_unlock 133.250s 3513.818us 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 151.040s 3012.218us 3 3 100.00
rom_volatile_raw_unlock 108.030s 2461.659us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4970.650s 18196.261us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5343.690s 20888.887us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 876.560s 6291.789us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 876.560s 6291.789us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 876.560s 6291.789us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 472.000s 5049.629us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 1958.640s 30657.556us 3 3 100.00
chip_sw_otbn_mem_scramble 472.000s 5049.629us 3 3 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 666.920s 7000.583us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 246.430s 4063.421us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 1958.640s 30657.556us 3 3 100.00
chip_sw_otbn_mem_scramble 472.000s 5049.629us 3 3 100.00
chip_sw_keymgr_key_derivation 2435.720s 14837.770us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 666.920s 7000.583us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 246.430s 4063.421us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 593.980s 6763.741us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 315.340s 4097.949us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 310.590s 3572.455us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 903.590s 9580.203us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 836.940s 6763.472us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 771.410s 9881.693us 0 3 0.00
chip_sw_lc_ctrl_transition 1134.690s 14594.310us 15 15 100.00
chip_prim_tl_access 741.640s 12717.219us 3 3 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 741.640s 12717.219us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1042.570s 7452.873us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 302.460s 7276.195us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1544.860s 27459.776us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 383.610s 8555.939us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 585.240s 9925.783us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 810.280s 9083.520us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1776.320s 28541.287us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 6 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 607.360s 10508.936us 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 641.900s 8785.513us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1350.520s 15762.786us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 540.290s 5116.224us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 302.460s 7276.195us 0 3 0.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 380.650s 4141.354us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 3 33.33
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3595.940s 38226.184us 1 3 33.33
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 538.140s 9762.521us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 272.800s 3614.977us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 744.600s 11470.851us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1127.460s 9548.200us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1731.100s 12389.685us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2536.070s 33513.446us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 279.790s 3461.195us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 553.110s 9359.613us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 553.110s 9359.613us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1731.100s 12389.685us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 744.600s 11470.851us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 540.290s 5116.224us 3 3 100.00
chip_sw_pwrmgr_smoketest 452.470s 7668.749us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 497.140s 4646.663us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 543.740s 7310.515us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 478.290s 6399.535us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1668.790s 16397.693us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 307.280s 3794.018us 3 3 100.00
chip_sw_rstmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1292.410s 8083.811us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 650.230s 5708.342us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 680.470s 5256.541us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 274.450s 3082.814us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 246.430s 4063.421us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 543.740s 7310.515us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 543.740s 7310.515us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 235.010s 3732.096us 3 3 100.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1378.490s 16352.076us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1606.310s 17344.508us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 497.140s 4646.663us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 310.200s 4087.847us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 1850.810s 13265.184us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 585.070s 9448.788us 5 5 100.00
chip_rv_dm_lc_disabled 1 3 33.33
chip_rv_dm_lc_disabled 575.270s 14720.753us 1 3 33.33
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 711.060s 5695.603us 3 3 100.00
chip_plic_all_irqs_10 386.650s 3853.354us 3 3 100.00
chip_plic_all_irqs_20 517.030s 5629.657us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 283.870s 3659.150us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 272.570s 4207.400us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 4103.090s 15112.807us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 407.460s 4323.288us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 285.160s 4310.145us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 388.230s 3712.881us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 283.600s 3896.768us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 666.920s 7000.583us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 567.990s 7007.181us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 728.360s 8179.000us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 836.630s 10655.762us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1038.600s 13290.250us 3 3 100.00
chip_sw_sram_lc_escalation 93 106 87.74
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
chip_sw_data_integrity_escalation 714.200s 8049.209us 6 6 100.00
chip_sw_sysrst_ctrl_reset 4 6 66.67
chip_sw_pwrmgr_sysrst_ctrl_reset 1127.460s 9548.200us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1583.910s 24311.850us 1 3 33.33
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 283.300s 3915.693us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 361.800s 5053.240us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 564.030s 5356.546us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 3 33.33
chip_sw_sysrst_ctrl_reset 1583.910s 24311.850us 1 3 33.33
chip_sw_sysrst_ctrl_sleep_reset 1 3 33.33
chip_sw_sysrst_ctrl_reset 1583.910s 24311.850us 1 3 33.33
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3177.890s 21019.994us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3177.890s 21019.994us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 575.740s 9014.071us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.178s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 200.590s 2953.191us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 248.350s 3179.005us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 373.450s 3805.002us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 508.860s 5364.831us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1377.260s 8281.429us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 7580.370s 32505.893us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2661.740s 13140.365us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 249.440s 3929.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 320.060s 3960.757us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 248.070s 3709.961us 3 3 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 15592.730s 68578.065us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1586.980s 7367.054us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 296.960s 3630.175us 0 1 0.00
rom_e2e_jtag_debug_dev 667.470s 6567.229us 0 1 0.00
rom_e2e_jtag_debug_rma 245.060s 4934.846us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 144.630s 3541.292us 0 1 0.00
rom_e2e_jtag_inject_dev 116.250s 2351.609us 0 1 0.00
rom_e2e_jtag_inject_rma 103.420s 3434.641us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 95.566s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 405.600s 4418.023us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 521.360s 3179.934us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1536.140s 7142.205us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1479.280s 9194.358us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 338.710s 3206.332us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 856.540s 6143.266us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 244.300s 3522.546us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 255.730s 3632.816us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 573.790s 7592.919us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 526.260s 6531.280us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1731.100s 12389.685us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 296.960s 3630.175us 0 1 0.00
rom_e2e_jtag_debug_dev 667.470s 6567.229us 0 1 0.00
rom_e2e_jtag_debug_rma 245.060s 4934.846us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 2 3 66.67
chip_sw_rv_dm_access_after_escalation_reset 598.750s 6723.410us 2 3 66.67
chip_sw_plic_alerts 87 100 87.00
chip_sw_all_escalation_resets 699.320s 7454.509us 87 100 87.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.184s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.184s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 330.320s 4770.981us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 528.130s 4816.301us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 4092.600s 19386.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 31 54.84
chip_sival_flash_info_access 310.890s 3824.978us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 33.040s 10.100us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 9.130s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 248.640s 3884.668us 3 3 100.00
chip_sw_otp_ctrl_descrambling 312.090s 4202.047us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 341.280s 5342.602us 2 3 66.67
chip_sw_pwrmgr_sleep_wake_5_bug 11.990s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 302.150s 3871.379us 3 3 100.00
ate_bootstrap_flash_erase 778.060s 10010.160us 0 3 0.00
ate_bootstrap_one_frame 9780.270s 44548.914us 3 3 100.00
ate_bootstrap_disjoint 10800.188s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 34222672215537989475832272581144644521948314636394477764341535416766411724674 309
UVM_INFO @ 3011.028120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12069702958648893542952672381858442522423431837956572090204754641312926132566 309
UVM_INFO @ 2951.166120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20636058852535280527655634575668980675657771502676096144909652488742510239250 309
UVM_INFO @ 2870.311480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114420569373485464717057595406313505544592900651943963484779913457554738243222 309
UVM_INFO @ 2931.799131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71150513655431562073029983498906233822012530039955551252915521433329850808867 309
UVM_INFO @ 3539.529802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60828086466129797396098198379447986821181229219239304618042052598876872495224 309
UVM_INFO @ 3883.782264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20323039632147670474999377498407020426359994107973478150253525563708332951162 309
UVM_INFO @ 3137.316224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97934592277259501155003642310048512642494758931915087944174147666921817351596 309
UVM_INFO @ 3878.443590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49853826845522257971569657515078939969353291225779710346133893521921039652640 309
UVM_INFO @ 3658.098860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14090527686522752682621062013899072961286514655048759135622740186564155342823 309
UVM_INFO @ 3474.783080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114879543853651184466528960722825806988323717614042918595683427062959141480236 309
UVM_INFO @ 3103.623640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78525127415049736117272858033887510780057950689260698494669161910864537158663 309
UVM_INFO @ 2751.020528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 105972701676460574608062115658990007084361071891800845796025205091882907854950 309
UVM_INFO @ 3076.547055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56687629751730476135502657073796566692337001276975362030597742262787303029671 309
UVM_INFO @ 3528.411777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112395349726616690360653194854045430310485774440404003908616142978998232988487 309
UVM_INFO @ 3693.640964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87765234316317895039884248342319687606503776689449073072030932846613010420318 309
UVM_INFO @ 2509.100904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86909719095716335771252372697915821635741922882528413022878610389191815554365 309
UVM_INFO @ 3770.928000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93604750968032831305038058062923568361077532196080395392313880791627570022061 309
UVM_INFO @ 2854.201042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29164432915352911516019831118095716323110386347240659151289186252134639771850 309
UVM_INFO @ 4083.736904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102975586012175443194275437225157836249042908812312834099028408834151610726465 309
UVM_INFO @ 3664.854440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81363762630776504117789297495813892195844290673682727889965036778612949027326 309
UVM_INFO @ 4470.760352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85048804479805089873164436963357255253476539048857161708163490444224269061228 309
UVM_INFO @ 3612.792400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106246588221941213340989463986266596370916820174787648662654619605156501511712 309
UVM_INFO @ 3483.945747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29355299806594316067736762355652322003496893469800443089773551929285346791764 309
UVM_INFO @ 3453.006312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108103842066537769968950848955865393530897831737147899690338093929110610241996 309
UVM_INFO @ 3734.321494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30599778601677063240867081969200254827130800853878239478288498368967760591860 309
UVM_INFO @ 3763.783272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18853644505160045844290548215751181272263303436425036800434175531879789412984 309
UVM_INFO @ 4273.873113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27164224828597763558407470399570497052578281415761465648047960629740594063823 309
UVM_INFO @ 3985.534852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43468334165409166594605325917722095138816528497541068447789179311371830718825 309
UVM_INFO @ 3176.206942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27611540484252166224040430200585481237673280601929245370485898652685944009820 309
UVM_INFO @ 3929.823800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72021979021170621305477902991898333694008842814913730591920035150383605577581 309
UVM_INFO @ 3732.265056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20121481044698767283003182568221704585517859206436084274333624256431796561355 309
UVM_INFO @ 3304.259380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 472359894208155228924480367965770499538472317955862383934026239889859597554 309
UVM_INFO @ 3341.611542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79499788657044242366331856818823125424402334954773600407231184512311490864807 309
UVM_INFO @ 3590.163717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29100971049470596134076823755916551790825382302188745555918506833634486212615 309
UVM_INFO @ 3433.366120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33652996031296399099464421373772602207012969568419691896898007188491501164554 309
UVM_INFO @ 4071.561096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2028264496157414579044266648958034561948410022695740774843425956723427158994 309
UVM_INFO @ 3830.843836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28817461552618669787422138054023331811009512635910439392992832299902304243214 309
UVM_INFO @ 3469.834014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112062242525927436907133507427381226264576603136866955567501448713566302688678 309
UVM_INFO @ 4305.044115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37409160488913224382096100685724201356099596487800093974327719752590715614446 309
UVM_INFO @ 3552.197296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15115509891399364623468331566705660534349737480050135880300777814291621147647 309
UVM_INFO @ 3812.100373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44776506562210713105145704274108016917256673644951019656338284752923897222563 309
UVM_INFO @ 3033.973109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88320247455431160979592705855161824840879265512337046792711340847546753554633 309
UVM_INFO @ 3369.673332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19326583189878758216608571757295181249586441226550660851825357954625772827101 309
UVM_INFO @ 3200.583438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 105380620618407060843860696287934489918112656327139825539376631780903197574858 309
UVM_INFO @ 3219.906555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45731175786279158267956406318472921195805230853554721265721029400523935276231 309
UVM_INFO @ 3694.954388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54511835115550250544580752793964729891132048906873717441876642917441353293955 309
UVM_INFO @ 2806.251090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59178487071616179566352872161725345260772771746939089609224344645808737115989 309
UVM_INFO @ 4356.336050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20006092869398313324793808757763959312256552860451934186860740184658777902218 309
UVM_INFO @ 4284.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8826033111828141895800694764076089342439296823942390284420454662003306322756 309
UVM_INFO @ 3349.862600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99762392602175118954540503043590562798020488314873813004566537074966347585579 309
UVM_INFO @ 3551.969324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63613832761560154545147429046459839579351784207225788993892804143963915895874 309
UVM_INFO @ 3897.307496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34899337428878462618889219587286777659988360537248619249769048796060308320001 309
UVM_INFO @ 4060.202444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61891348526412610470020103664503964238689912762996862696950144806739128615393 309
UVM_INFO @ 4111.340754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115468707347939037096150272351285066920131710102062180904160756752317797006819 309
UVM_INFO @ 3410.299283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48090909287739271520568758375239998984885496166662496987091577969620116394224 309
UVM_INFO @ 4025.282510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25255592679665262309596656025519983267067275119602515901234082829400971778844 309
UVM_INFO @ 4218.371840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11807706349535421147576623435806274519195921574676532538735884056970320488414 309
UVM_INFO @ 4155.494972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49417023992569009244081738832137804485802439894866470857140900721502557063822 309
UVM_INFO @ 3497.591176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74971277383342207807690523867665031962341014599131047831770201997678123820989 309
UVM_INFO @ 3034.142680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52648492387346320515107167881609056346813356486958280387414878312834586476195 309
UVM_INFO @ 3052.506566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3125525316252934755966564214351876093418080243910939892136559746111758440002 309
UVM_INFO @ 3127.147528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55153429543162985798612963960180273977616733638971555862867177159268504587277 309
UVM_INFO @ 2885.485640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35853098763826351613218448929323811420656114566659595902503463919490801924521 309
UVM_INFO @ 3098.735804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46659645606422960170909847414847602542451586434222525445253405758364549749751 309
UVM_INFO @ 3444.144801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89460882984516158039288984797550604153089151721275028204688950166748111152723 309
UVM_INFO @ 3516.606196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87436691644877482724683675481842447996098813965440743797287520511386669391343 309
UVM_INFO @ 3798.945296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62973073888691420403809761627764654676638663182477544693750248486164584909012 309
UVM_INFO @ 3678.938614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33076915038053657126917921556830074601340773291098953925890589898603254418285 309
UVM_INFO @ 3121.562968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53747108034014391426195122944428936006691164949326966596690666009873897917693 309
UVM_INFO @ 3654.038102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78995048535013390404062442043307208642291115798529706953014051315610865437703 309
UVM_INFO @ 4120.895915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78843572504269626141670087938303534614522549082805993295948175099990781055981 309
UVM_INFO @ 3455.513036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51851487060350092423546835983311144201415935199189147195290999075567721667283 309
UVM_INFO @ 3126.231699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103533461933359788328519053533255567410367619242265318533828658418885726456738 309
UVM_INFO @ 3534.008878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62609007256959632603774460482962324180972279678438259409941737423249841953773 309
UVM_INFO @ 3726.599836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84499322698815955470983381389095308129467653513011737511551979361745873834246 309
UVM_INFO @ 3389.438336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77132495151026676968343042498908711740917525003287618898493961695719835399300 309
UVM_INFO @ 3835.351040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36472507931617215921168172122683920558264720508879376538380786249816399647463 309
UVM_INFO @ 3778.396967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19513002226538586781306298704504180664799419108234777683382239186563826727343 309
UVM_INFO @ 4312.290390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5842227476101998222811920576638012785787898559252058012213573760911554512306 309
UVM_INFO @ 2952.810650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93121321335176215490332321305608439239674858225608270230588932916317509333411 309
UVM_INFO @ 3016.338872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34651501213308701336893070615976855738847626767094241149365702657543681652861 309
UVM_INFO @ 2936.254748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27833177804286397861331356883773208061445760722518068413039791181641951955870 309
UVM_INFO @ 3454.633264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44773349042381907441062569939804077654130260090300564949623931658542759833255 309
UVM_INFO @ 3940.145436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102170992321102720271376908706640901841455925606366969662413832718176711218846 309
UVM_INFO @ 4142.754583 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112775949430471372140336963523031643733390277248216232430794086854971260954063 309
UVM_INFO @ 3239.602976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88547142494486909520723694299149065383168878611917197035080351076558063494443 309
UVM_INFO @ 4143.267816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71876729578692569384114746157164069926423574603082592220790300676884913865786 309
UVM_INFO @ 4020.538496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39072958448670032119283617470740427424748062438031988567653659418768218402862 309
UVM_INFO @ 3923.408110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106662530073957008103421225734009706946791191517306274570897901544584869771222 309
UVM_INFO @ 3190.606520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 31 test runs
chip_tl_errors 91594881653641395668087470031835529404390039885833183065916895030047252967467 218
TL item was: req: (cip_tl_seq_item@30576) { a_addr: 'h104b4 a_data: 'h818363e3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h195eb d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2792.437006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 50248693964169931405517543937575371214460211628604642912455429219688133744934 225
TL item was: req: (cip_tl_seq_item@30994) { a_addr: 'h104a8 a_data: 'h7bc0da33 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1a909 d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3695.069049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 4176657978839797362045961451651110215405564168510751897679889456315117130396 218
TL item was: req: (cip_tl_seq_item@32788) { a_addr: 'h107a4 a_data: 'h5d998364 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1bd71 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3186.820637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 56873771652449524898986455603194678279097298579840266775736874449692935333641 225
TL item was: req: (cip_tl_seq_item@30372) { a_addr: 'h10794 a_data: 'h4b56eb67 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h18144 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2722.504754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 82847917717963341842841114370730849024108329149007984946058429423232216509911 223
TL item was: req: (cip_tl_seq_item@30686) { a_addr: 'h1035c a_data: 'hcf6edf1b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h19e82 d_param: 'h0 d_source: 'h38 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2626.375470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 75872193790766988331684030701485746480832267708042611081178295971042004368942 225
TL item was: req: (cip_tl_seq_item@30604) { a_addr: 'h10480 a_data: 'hd5275f9c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1a514 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2816.698775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 68101537337942087461080358604372470022598646015329776502572780195286130484115 218
TL item was: req: (cip_tl_seq_item@31280) { a_addr: 'h104b4 a_data: 'h6288bfb6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h195ba d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2379.346345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 92886722050611297301583359761197968026564753887894620015156376438012817304712 225
TL item was: req: (cip_tl_seq_item@30392) { a_addr: 'h104e8 a_data: 'h7c4254dd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h181a5 d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2929.964720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 29051991167201728067133160760012876570780842178406046965215964317909406799162 218
TL item was: req: (cip_tl_seq_item@30590) { a_addr: 'h10524 a_data: 'h535232f4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h186a4 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2777.538215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 5033157048683797302494749871592956781242742220527478332892600342830923662593 218
TL item was: req: (cip_tl_seq_item@37532) { a_addr: 'h104dc a_data: 'h607a8b62 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h1b11c d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2575.189296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 66977015871852586125997704368570486427753062599307202776688185329462245173145 218
TL item was: req: (cip_tl_seq_item@31408) { a_addr: 'h10724 a_data: 'he0e3915b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18dc6 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3314.085639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 83424629133089168753518575211333175825901005605502194033759152211229334606305 218
TL item was: req: (cip_tl_seq_item@31366) { a_addr: 'h10728 a_data: 'he40dea0e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h19591 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2609.377348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 38004909951789168133752723707849835889463912195606289524771589158532245974410 218
TL item was: req: (cip_tl_seq_item@30700) { a_addr: 'h107ac a_data: 'h38277cf2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1a9e6 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3677.664144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 27164173797875737123672298522266050135823149341746767632159993256801910858701 218
TL item was: req: (cip_tl_seq_item@38334) { a_addr: 'h10368 a_data: 'hbbea86b8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1ae26 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2776.609909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 13441481610152310880150275616172997371894265136254818474426018858801958643909 218
TL item was: req: (cip_tl_seq_item@36424) { a_addr: 'h10518 a_data: 'h4a43bb90 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1a2eb d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3524.682529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 33958186194076243116305949314161582988039738144235691993741155106725151985768 218
TL item was: req: (cip_tl_seq_item@31416) { a_addr: 'h106a8 a_data: 'h17c598fb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h1a24c d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2528.604148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 81791558360921785266055477487811220701325788900159205353243308124179019581430 218
TL item was: req: (cip_tl_seq_item@32698) { a_addr: 'h104e8 a_data: 'h9d903e7a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h181f2 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2820.987893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 87761796784656307096221174763470775133123781014086675900329754971276633701253 218
TL item was: req: (cip_tl_seq_item@33478) { a_addr: 'h105fc a_data: 'h15da165a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1aeb6 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2728.875704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 10202960939728277432424077736060004744030956805974700675221686151687859416612 219
TL item was: req: (cip_tl_seq_item@40370) { a_addr: 'h10384 a_data: 'hbf72dad a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1b6ea d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2852.921218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 73725156674135773140447494234954120570852992195145414825557090684458070115992 218
TL item was: req: (cip_tl_seq_item@30598) { a_addr: 'h106c0 a_data: 'hc3086291 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h186d9 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2812.974955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 52711491628721212135059657117842527528400358190928622800677520636970740328627 218
TL item was: req: (cip_tl_seq_item@32672) { a_addr: 'h106d4 a_data: 'h926ce84e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1aea4 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3595.694784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 70933245154283517564671567296573537609704278193953395152912206479765318919774 218
TL item was: req: (cip_tl_seq_item@32146) { a_addr: 'h104d4 a_data: 'hf4a4e8e8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1a5a3 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2815.446615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 106129727229005848789011419034043246751149022653978105764405804476782142922463 218
TL item was: req: (cip_tl_seq_item@32094) { a_addr: 'h10764 a_data: 'h2443d3dd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1a534 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2826.143367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 108146786042033791852089555607673049563999996251700489002042088011694505443092 218
TL item was: req: (cip_tl_seq_item@31594) { a_addr: 'h1057c a_data: 'hd3d9609f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h19e32 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2707.019538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 33458224219779851782966580529372113348915365838759521175259456770131280816398 218
TL item was: req: (cip_tl_seq_item@31378) { a_addr: 'h10450 a_data: 'hfae533cc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h199a7 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2905.088526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 38724631127303655923707071889141095372773638668980068312983450446201365913438 218
TL item was: req: (cip_tl_seq_item@30462) { a_addr: 'h1059c a_data: 'h76875583 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h19edb d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3633.812247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 15504905667437278130041782506977368087651591982611780902284138039704570137675 218
TL item was: req: (cip_tl_seq_item@30474) { a_addr: 'h10354 a_data: 'h57899aa3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18a15 d_param: 'h0 d_source: 'h39 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3180.630266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 112274012494094448723500823798581785924780927052864239066058825239689715337150 218
TL item was: req: (cip_tl_seq_item@30654) { a_addr: 'h1076c a_data: 'hc024016b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h1b1c6 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3108.534841 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 67589158306821246039531139770852381729032519377741748978827943265316639057625 218
TL item was: req: (cip_tl_seq_item@32222) { a_addr: 'h1056c a_data: 'hab9e3408 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1baed d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3325.290570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 4438966626634035990437682050793500539192711913741890024286284620112516210274 218
TL item was: req: (cip_tl_seq_item@40448) { a_addr: 'h1078c a_data: 'hcba87471 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1b154 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2958.734905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 24493655343603108715771760350033472285773128656219544555757716247965061547865 218
TL item was: req: (cip_tl_seq_item@30472) { a_addr: 'h107ac a_data: 'h7f0831cd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1a988 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3387.968851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 15 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 114601991607524169920904091925917672894053684227032213348027255930049875712792 316
UVM_ERROR @ 6140.789000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6140.789000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 41015714735539851773423667562294611893626598302283066665876069444113157524503 315
UVM_ERROR @ 6343.675500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6343.675500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 32482310947993952217233382506595730374508836470270421480381397301389621800842 326
UVM_ERROR @ 9457.371000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9457.371000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 39266950507096556776412309651133598258450382601068454770664238755895731215725 371
UVM_ERROR @ 18501.933000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 18501.933000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 7858656919003183649558708076665259073327786519305234742646617713340841442729 335
UVM_ERROR @ 24311.850000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24311.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 55550782091846756708825788809012857320419630083053789268667480986779701453871 320
UVM_ERROR @ 7571.655000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7571.655000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 47952541987626129282920229739212653024641510390251317940432575577611568886044 316
UVM_ERROR @ 7038.301000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7038.301000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 83074119527628244134539650401446591702814479058097220049194471647753869765311 315
UVM_ERROR @ 6571.036000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6571.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 33876507311294723005248851164132197223317610818251780534805959207528683926835 326
UVM_ERROR @ 8626.668000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8626.668000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 87840163420551554714561080491004900611414406571699364705065831292208639390577 335
UVM_ERROR @ 24631.278000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24631.278000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 99753040630499052439077606860738159216096706946693703576093076680544231615526 320
UVM_ERROR @ 8367.716000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8367.716000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 64149152375396426288645446772376439980031794115012151293777860847795437466134 345
UVM_ERROR @ 11470.851000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11470.851000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 13885084249762540977011042857833288199280008843444706324274677632953473071108 328
UVM_ERROR @ 10508.936000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10508.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 92825339889332420211159867195976929533360275208959881622087665755367958091308 326
UVM_ERROR @ 9925.783000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9925.783000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 84876604137486594714668986293287383359668258888804767147367770962207704687911 320
UVM_ERROR @ 8785.513000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8785.513000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 13 test runs
chip_sw_rv_timer_systick_test 115083886042914950294509185264407841807479636924316971625484461850746769696038 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 73923352861968900239597259179920230865447434298684552068605072678218238223549 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 75836650384557891297522074222983933793322906428731694375866876357230596065173 None
chip_sw_alert_handler_lpg_sleep_mode_pings 85902393402166764399203189855338032920327787380235393596827902928341054198697 None
ate_bootstrap_disjoint 115337611539336221195075123214597149625941797030648097415846315731703855621028 None
chip_sw_rv_timer_systick_test 9696587969936656012009493972568865749118547085849936525152693783279456338414 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 105105050455166976358728243093308121713497426541858376506520379229785523837082 None
chip_sw_alert_handler_lpg_sleep_mode_pings 69124462742063272063047797490302119893619436567009699962871818310151973208490 None
ate_bootstrap_disjoint 110917951773525291309367267585165647660316750689773243394467653062524083148331 None
chip_sw_rv_timer_systick_test 17436579984518763077909433175240558139333600530806299636880595554117990247109 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 10720828223357868484989708772666972594660378583098141923702811060618866462361 None
chip_sw_alert_handler_lpg_sleep_mode_pings 55185193170524378620486432191772852360664220041371634817044811158337302154004 None
ate_bootstrap_disjoint 21805437736595895847283843847025353103729081657549051431759336876782147002141 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 8237586889893674022504307062460342661947762772965926344581024613228080131453 370
UVM_INFO @ 12707.634035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 48735256400397695085945900470915659972051735591614937126360663107164391227229 370
UVM_INFO @ 14001.918374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 84003371747522398189629759910020723888627082564860526527427678890539739862085 342
UVM_INFO @ 7935.141794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 34999908303955932961980782287970636400665569022887577863542305832316436429686 370
UVM_INFO @ 10626.540386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 6724351948127827542484944652943695472844533895128277854794277420743211315019 370
UVM_INFO @ 14162.945176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 32824836026883821335735215733327967033358820086991436848759013691413569861433 342
UVM_INFO @ 7376.558298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 104807482691971282481260475360574302683803163280900424718932056658177964125455 370
UVM_INFO @ 12338.269007 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 37039524638396931000928433976748473203691915839271664854223353695814696218759 370
UVM_INFO @ 13618.927440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 12656609933410947141208255166600662963646481576373702316701485531909354620902 342
UVM_INFO @ 9400.445024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 9 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 6481516774124264825155227742761655477083043686338393835069256387133269415558 328
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 46686318867307796510914423777315869190088810917528098141134384986419216881704 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 35878281220031151462462038231066776884037464526799278291480513940283614306953 353
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 33428949440220461390181856978229060685683861080448622754336560778993253511121 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 104946642727039043373936060166057711667173062653800916354076677118874526156710 304
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 59149653514979946401672318845744662265741328198586328103118289108233147429120 304
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 97816427555527379988664496437629494023312837371568209172897426819288729877576 304
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 75154901476030610116201491148692740036831958260670078232476257783486927937100 328
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 84595914508219527017195153532270959329203964481977592661906547623291951195464 328
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 6 test runs
chip_sw_otp_ctrl_escalation 48549445463435354985603960157807164212011837794478441593350599622927394894284 317
UVM_ERROR @ 3632.815842 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3632.815842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 78216443739025249269861901561953420066165325308624183007382626116035388996155 313
UVM_ERROR @ 3743.712474 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3743.712474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 38290060977828159878261781954410387795974261663728468127927589896397820828560 318
UVM_ERROR @ 3615.281864 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3615.281864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 4310129866592068430106513927809751520069377976943731266278004303056239262172 318
UVM_ERROR @ 4017.232014 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4017.232014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 30917898155406931262024196804197821978382347452219232567790427445674936574689 318
UVM_ERROR @ 4067.289264 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4067.289264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 37375071399055174298503925225055472502206560229415384507737200049106755731789 318
UVM_ERROR @ 3787.638890 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3787.638890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 6 test runs
chip_sw_hmac_multistream 36614934349068031174240488916928894114411127185489178252854839103879497257409 371
UVM_INFO @ 12018.701411 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 102542561882544697802390249779772842237624061410896513171210836395384548738835 337
UVM_INFO @ 20018.667254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 104382540816034814871618412238481338187063039343280342275709451986151332863977 358
UVM_INFO @ 12018.432574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 99163905870961983493692542779244699871060496261683470921617559172439473891600 335
UVM_INFO @ 20026.705017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 41066139206010965736566345255799451263471236247739816580407862226264898164282 351
UVM_INFO @ 12018.350009 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 98777798961135364456366596004526601969128541672881162470339434933618735892601 337
UVM_INFO @ 20018.539128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 17516502714951362327135414994483998665452289339897894589379556051045936034714 None
---- STDERR ----
Another command (pid=3548563) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=3548719) is running. Waiting for it to complete on the server (server_pid=254264)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 10737956995340434932703951469821638784441396816451433114032525440222966330520 None
Another command (pid=280150) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=256524) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=281374) is running. Waiting for it to complete on the server (server_pid=254264)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 52051998137638712363421141324364650462144208554283037148727666901821300576037 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 100083602782769386590736215400408010135466312888807028073955032024306808384907 None
Another command (pid=293269) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=295474) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=296504) is running. Waiting for it to complete on the server (server_pid=254264)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 99745037027006450980580648601288518435930275844552024985978914830961292985867 None
---- STDERR ----
Another command (pid=1239620) is running. Waiting for it to complete on the server (server_pid=254264)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 51683189799082347424831752500789515124759533435969045723420958080707827682290 None
Another command (pid=337752) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=323497) is running. Waiting for it to complete on the server (server_pid=254264)...
Another command (pid=336639) is running. Waiting for it to complete on the server (server_pid=254264)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1095)] Unexpected fault 5 test runs
chip_sw_all_escalation_resets 103295829612729746655802317735710042714968569905411447017437096262563451031304 311
UVM_INFO @ 3437.911120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 65132499306287886748936025447729915449075092441246922113026784944628607268469 311
UVM_INFO @ 2787.492770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 50200028937864900651745905296366524111610238649612801725164399434009672589297 311
UVM_INFO @ 3281.583975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 29742199209574836485374752943944561762490566676200190221230153865529289434629 311
UVM_INFO @ 4036.553880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 26817784134837440864266658645210774107350499435516095255310662325017662352342 311
UVM_INFO @ 2582.334904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 4 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 48325770381640272558916662763735173520532392873422288788591339138606620282628 314
UVM_ERROR @ 3614.976891 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3614.976891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 74298050457023024710329940405312801609273657174034821560919066489432406303667 314
UVM_ERROR @ 4027.172160 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4027.172160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 109335851452151083016746612174566688139222996248346063651510661298344520759611 316
UVM_ERROR @ 6114.894755 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 6114.894755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 96903170184856025675134661674110388895743629625267225064043246533022855746345 314
UVM_ERROR @ 3427.731448 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3427.731448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 92305694720327885850794202312769037979635142283215346522978595394818996911532 302
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 65428626086336517448290820713060049995956910637310463377646294445535112822008 302
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 35599365445574741727018192851030744564316212020778443394783171476199889537671 302
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_flash_ctrl_lc_rw_en 80178661635270983376426177770457793593699631516397824125556648952793056193320 310
UVM_INFO @ 4193.039745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 13427199244399188858172525568032952920094368994191189349906135820111309990063 310
UVM_INFO @ 2802.990825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 6872867662812255979079096741577461512284957078097870489984134043280713129661 310
UVM_INFO @ 3974.065868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 3822755318061833681014951302963480899899591217854610165846077122911939927436 343
UVM_INFO @ 9881.693248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 93134555427082416873823544230201490297370753925415737338435064283367066218172 343
UVM_INFO @ 7604.183650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 19837173939807261770076095224461063980002481088700275838982626160735471596434 343
UVM_INFO @ 5859.954456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 3 test runs
chip_sw_pwrmgr_full_aon_reset 62416285940447729564994763557328024686840647325280884097559692967939034734794 304
UVM_ERROR @ 2705.182470 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2705.182470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 69709404333710894200365630014271127500384402780903243470912790832555474299056 321
UVM_ERROR @ 6189.814424 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6189.814424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 44647978523192600384882168428619344690684200051124536439569535027268855771372 321
UVM_ERROR @ 7276.194699 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 7276.194699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 112941486751678234274091186635033819570585380683222303344013175636335610522087 344
UVM_INFO @ 4108.237948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 34164000169208942401788480455309707268894446902813316635498494209010087191368 344
UVM_INFO @ 4065.575087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 12803564844158059960793839147885474846539136509805118431807119048990646960470 344
UVM_INFO @ 4418.022729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 3 test runs
chip_sw_power_idle_load 61536463856479523862999398495364223369067933567375263236015025667131806331346 319
UVM_INFO @ 16300.754672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 55835932480823916921517828615719447764167719495590335720008436151498209262446 319
UVM_INFO @ 15561.998480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 92326825316019513368366485411310718446533644068834213961796839089631921791618 319
UVM_INFO @ 15280.864104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 3 test runs
chip_sw_power_sleep_load 17445599111597885146434270097227420075930418928078037352875592807525323074228 330
UVM_INFO @ 14979.920192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 37003666348663092215851460081143306424603158485052772045523963325917143725678 338
UVM_INFO @ 15023.992712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 54575385217497145510700854693339651114978812124790605139859422130839710273348 338
UVM_INFO @ 15305.848724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 65232741664850320598991895332795303847522608391518123573555605203490257580813 328
UVM_INFO @ 15358.289428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 68587996203455448471150190310014745829172552948115656116067318336945317738830 328
UVM_INFO @ 16842.815787 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 51773169296478517327436656141333541789522985283539409812664989378272062674887 328
UVM_INFO @ 12755.676033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 26820053273632624456385168950166935438689092376200267375542466733970504301520 273
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 29532772879352097006530544597100741264910085488247190102163789371155630721633 273
UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 108291381355967726729734298498552240319411328570467277134034103530652178042103 273
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 3 test runs
rom_keymgr_functest 34765328542107232003248372767486090538463444102182390666501664862995853940907 328
UVM_ERROR @ 6345.133568 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6345.133568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 104333071053874871949280563453869146880493101805802575459025629380847631292478 328
UVM_ERROR @ 5982.731974 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5982.731974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 108084054873020014016326923236934570815615937027399102110871434051024323726347 328
UVM_ERROR @ 5045.007802 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5045.007802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 2 test runs
chip_sw_spi_device_pass_through_collision 14381053476807840524934577375232355167032546844697146896954205032742390313600 330
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
chip_sw_spi_device_pass_through_collision 37676791928825140629178172802984055147858225128186676180819627027257240924037 330
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:376)] CHECK-fail: Expect alert *! 2 test runs
chip_sw_alert_test 49454942289311107301832778167094745651408275517595863416982599332433650406481 308
UVM_INFO @ 2899.398880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 23114985257324457642124974971146378973193487140254969902858757464331637071859 308
UVM_INFO @ 4278.346234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 2 test runs
chip_rv_dm_lc_disabled 12698715410077590011973963792613898077431365694135943966648531707446194591572 226
UVM_INFO @ 5534.011810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 23658849778370704146013595830539307007108943684272714445411235317085489904786 226
UVM_INFO @ 4569.029047 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 2 test runs
rom_e2e_keymgr_init_rom_ext_meas 43816559789347824799632163853919403159250500066063679014948591702608184437266 320
UVM_INFO @ 18193.336047 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_keymgr_init_rom_ext_meas 53871681656975027774728097710986638493680378702591549901928493466574985244476 320
UVM_INFO @ 16622.498454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. 2 test runs
chip_sw_all_escalation_resets 78474268477953963701542841023105819007939903828060890522882910126220523739467 317
UVM_INFO @ 3762.866424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 3555030859624360526847388745871085219457859409810211275152226279066371327864 317
UVM_INFO @ 4031.614546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 2 test runs
chip_sw_sleep_pin_wake 64187206667569219703675955620509841586846908789080444719147094925262806428999 319
UVM_ERROR @ 3691.422000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 3691.422000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 106476352468168240969659696706894367363473575283038100219731216567363204482628 319
UVM_ERROR @ 3066.535000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 3066.535000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 2 test runs
chip_sw_rv_dm_access_after_wakeup 91836721783328762549645030129619598448517608682934009493157224541277934132308 330
UVM_INFO @ 13265.183752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 99817002251522325515381467390712724336514353984617251453642185936629425802051 330
UVM_INFO @ 13472.597496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got * 2 test runs
chip_sw_all_escalation_resets 21440168123478459623319392912257255538156560674078949504348095312475306508504 318
UVM_INFO @ 3392.231102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 43137363438612850068712550287283655281199601043195516630523532436326500480038 318
UVM_INFO @ 4026.369140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 87367924992529194755904187548141247396531318580307777458326129651621408941787 283
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 85437376600189779923020114772263827856548277322101195933966121732849192200178 308
UVM_INFO @ 3229.770568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. 1 test run
chip_sw_rv_dm_access_after_wakeup 52135279576439687080782306484190571074502312361222892618221486388049072085866 310
UVM_INFO @ 4195.300059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 67403351815798201070949019576978426192736291471350665473507597038172524872096 328
UVM_INFO @ 4310.145000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 4852212643766996847135578731734612041374202520063886293983072842806599239617 446
UVM_INFO @ 46793.775971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:346)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 98376173413493281968725358242314382833637151189135981524886571290260275473404 308
UVM_INFO @ 3084.373378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 106095187728225984007779342068895742095105071114350974667684572244444630804721 312
UVM_INFO @ 4213.443709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 49211416397427831989113178559972977085757377685487188346222478721456277801950 312
UVM_ERROR @ 4375.498616 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 4375.498616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---