Simulation Results

Simulation Results: csrng

01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.62 %

code
96.20 %

assert
97.16 %

func
90.50 %

block
98.53 %

line
99.54 %

branch
96.38 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.09%
V2S		99.14%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	28.000s	100.907us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	30.000s	45.152us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	30.000s	17.424us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	55.000s	650.191us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	32.000s	83.488us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	30.000s	14.191us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	30.000s	17.424us	5	5	100.00
	csrng_csr_aliasing	32.000s	83.488us	1	1	100.00

1282/1307 passed

98.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	54.000s	5402.367us	500	500	100.00
err				500	500	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
cmds				1	25	4.00
	csrng_cmds	3407.000s	200000.000us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	3407.000s	200000.000us	1	25	4.00
stress_all				24	25	96.00
	csrng_stress_all	979.000s	51769.818us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	30.000s	16.943us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	30.000s	37.343us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	22.000s	131.898us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	22.000s	131.898us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	45.152us	1	1	100.00
	csrng_csr_rw	30.000s	17.424us	5	5	100.00
	csrng_csr_aliasing	32.000s	83.488us	1	1	100.00
	csrng_same_csr_outstanding	29.000s	156.606us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	45.152us	1	1	100.00
	csrng_csr_rw	30.000s	17.424us	5	5	100.00
	csrng_csr_aliasing	32.000s	83.488us	1	1	100.00
	csrng_same_csr_outstanding	29.000s	156.606us	5	5	100.00

V2S

1274/1285 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
	csrng_tl_intg_err	21.000s	237.244us	25	25	100.00
sec_cm_config_regwen				20	30	66.67
	csrng_regwen	30.000s	27.308us	15	25	60.00
	csrng_csr_rw	30.000s	17.424us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	54.000s	5402.367us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	979.000s	51769.818us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	54.000s	5402.367us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	979.000s	51769.818us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	54.000s	5402.367us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	21.000s	237.244us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00
	csrng_sec_cm	29.000s	95.739us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	35.000s	223.075us	200	200	100.00
	csrng_err	30.000s	22.465us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				18 test runs
	csrng_cmds	45123443295530206831839290913749694728653121343443018172979107471516950070166	100	UVM_INFO @ 56141708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61986034758996488807506164803566743698460297555204043059234603396927409057636	120	UVM_INFO @ 361294502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15204849082865994464713432813255270857329914191597460994969760260065537848979	100	UVM_INFO @ 376923314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17021930372794444905700687931679743010674232168834674448156970878136724226236	100	UVM_INFO @ 30835370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107505911139066848492194245007746928810372881929952582300800269488055662749794	100	UVM_INFO @ 26087309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	860700196088224051290056270133693322436899980148857566052658124598519924192	100	UVM_INFO @ 160217552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33349920841990734971798974948166893144026005302058091744176150650543556365433	100	UVM_INFO @ 73113486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	26401816485379391017890296387095542414589673000615315932078200276606761785036	100	UVM_INFO @ 38852816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84900383385711990413449207693482008676574932696457346151628017232870051849294	100	UVM_INFO @ 99195652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82165942588570993344585401014137209500383495115745149938701831516442570466095	100	UVM_INFO @ 105520795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18293487628687029519201624211917922804721302698969451050157603376221334238496	100	UVM_INFO @ 790604037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	8806131573148586188810280402546642808466223879648384999554143321262997217469	100	UVM_INFO @ 47887161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107883474447951886233792648421387609124489782875643787934804671970114632839877	100	UVM_INFO @ 198057462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15060707072467240393669948049412014546027790484762245650440461652702466317284	100	UVM_INFO @ 151874287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103981217147989182745230545639470985766096767116044541785521672167385806860204	100	UVM_INFO @ 12499091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99399273245709440424464337651907047291891925857901270300024226322434504690136	100	UVM_INFO @ 21393664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	26850368035691508751881354672232047377212470200982934839405403489698521060176	100	UVM_INFO @ 32118363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14925311948614319659270890697491364706132215037649066706809861371347188034789	100	UVM_INFO @ 377283447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				6 test runs
	csrng_regwen	41065662735421973725089043051328116763813166635900627174417337943558676585182	99	UVM_INFO @ 12663417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	104083261649979779652921436689919584909263236193527388480883489044827438428047	99	UVM_INFO @ 6212726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	26912313353379309763095514214813032695361302069481485917743185419089357673759	99	UVM_INFO @ 2125284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	48424661398182167210717810679917219924595241437585551018091845573123811320876	99	UVM_INFO @ 1542556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	75163697697973678047415622764286419689863029310113270584005086538101438099375	99	UVM_INFO @ 3105670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	82807929644062474394187106201924497641757779555372199907670991611612287667254	99	UVM_INFO @ 2605136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	csrng_stress_all_with_rand_reset	76104217104356644049362157689353596924125256984846617834482064936187324386396	None
	csrng_stress_all_with_rand_reset	4264999760589628323892519822665123740478305194910316736930470058330093489755	None
	csrng_stress_all_with_rand_reset	4609243020431340450337873932764482807766854070529434892564763139008541459351	None
	csrng_stress_all_with_rand_reset	97226513395630467686689628045632433501761970186278463079099389665889232909132	None
	csrng_stress_all_with_rand_reset	30707812355364897573828282525864237595242134796858360540816761912420676681016	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				4 test runs
	csrng_regwen	87587643570241502158642148574469021837802687826112014595905422912496903936617	99	UVM_INFO @ 20427196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	26199410249708862001206694958057388308892950549872113628506886172570623853555	99	UVM_INFO @ 13112229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	110528063242506584236809805761445063358652138098336193375403712080875150631530	99	UVM_INFO @ 1586620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	23410871620401600571227875830926647170753014505409402331669851476966126180681	99	UVM_INFO @ 3783741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				3 test runs
	csrng_stress_all_with_rand_reset	82637344319565736995233902853838854553398781549486621516537164944866073782749	110	UVM_INFO @ 87395486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	27281269661661856412059447181806583641634881945354613219038279906518577927724	157	UVM_INFO @ 2408261858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	11208978612989829571044198694811739786181646721069499163493387570244998443991	115	UVM_INFO @ 60265449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				3 test runs
	csrng_cmds	81686941330610841130058752379964321631208539087651759570656834263626458736154	109	UVM_INFO @ 445407195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18341024193876460046930434864119840208636744473874574535941472584019516296298	109	UVM_INFO @ 74432582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6689668236352747811236834309207527697459044960173941283046375540915247372728	109	UVM_INFO @ 218613209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				2 test runs
	csrng_stress_all_with_rand_reset	7578608700936425728994628246739546822413611375250139913082730214617309259513	131	UVM_INFO @ 504560874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	110765331908819556728864461982824396383249550544100255967377229440242040636827	106	UVM_INFO @ 40896870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	csrng_cmds	73479580773416033444839867235403051233833565594277940119783561134978899821927	109	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	25971449701877237621879015059634804884436192969594394149297706704634149342900	117	UVM_INFO @ 370576284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	761039977608151580981321253024975377462586849486966662673541245007019024197	103	UVM_INFO @ 562792721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	34046698526056250131419966671019838913946262884231265076700720895875548882156	118	UVM_INFO @ 11810632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---